AD9854 Analog Devices, AD9854 Datasheet - Page 21

• Manufacturer Part Number: AD9854
• Description: CMOS 300 MHz Quadrature Complete-DDS
• Manufacturer: Analog Devices

In the Ramped FSK mode, with the triangle bit set high, an
automatic frequency sweep will begin at either F1 or F2,
according to the logic level on Pin 29 (FSK input pin) when the
triangle bit’s rising edge occurs as shown in Figure 42. If the
FSK data bit had been high instead of low, F2 would have been
chosen instead of F1 as the start frequency.
Additional flexibility in the ramped FSK mode is provided in
the ability to respond to changes in the 48-bit delta frequency
word and/or the 20-bit ramp-rate counter on-the-fly during the
ramping from F1 to F2 or vice versa. To create these nonlinear
frequency changes it is necessary to combine several linear ramps
in a piecewise fashion whose slopes are different. This is done
by programming and executing a linear ramp at some rate or
“slope” and then altering the slope (by changing the ramp rate
clock or delta frequency word or both). Changes in slope are made
as often as needed to form the desired nonlinear frequency sweep
response before the destination frequency has been reached. These
piecewise changes can be precisely timed using the 32-bit Inter-
nal Update Clock (see detailed description elsewhere in this
data sheet).
Nonlinear ramped FSK will have the appearance of a chirp
function that is graphically illustrated in Figure 43. The major
difference between a ramped FSK function and a chirp function
is that FSK is limited to operation between F1 and F2. Chirp
operation has no F2 limit frequency.
Two additional control bits are available in the ramped FSK mode
that allow even more options. CLR ACC1, register address 1F hex,
will, if set high, clear the 48-bit frequency accumulator (ACC1)
output with a retriggerable one-shot pulse of one system clock
duration. If the CLR ACC1 bit is left high, a one-shot pulse will
be delivered on the rising edge of every Update Clock. The effect
is to interrupt the current ramp, reset the frequency back to the
start point, F1 or F2, and then continue to ramp up (or down)
at the previous rate. This will occur even when a static F1 or F2
destination frequency has been achieved. (See Figure 43.)
Next, CLR ACC2 control bit (register address 1F hex) is avail-
able to clear both the frequency accumulator (ACC1) and the phase
REV. 0
RAMP RATE
MODE
DFW
TW1
000 (DEFAULT)
F1
0
0
Figure 43. Example of a Nonlinear Chirp
–21–
accumulator (ACC2). When this bit is set high, the output of the
phase accumulator will result in 0 Hz output from the DDS. As
long as this bit is set high, the frequency and phase accumulators
will be cleared, resulting in 0 Hz output. To return to previous
DDS operation, CLR ACC2 must be set to logic low.
Chirp (Mode 011)
This mode is also known as pulsed FM. Most chirp systems use
a linear FM sweep pattern although any pattern may be used.
This is a type of spread spectrum modulation that can realize
“processing gain.” In radar applications, use of chirp or pulsed
FM allows operators to significantly reduce the output power
needed to achieve the same result as a single-frequency radar
system would produce. Figure 43 represents a very low-resolution
nonlinear chirp meant to demonstrate the different “slopes” that
are created by varying the time steps (ramp rate) and frequency
steps (delta frequency word).
The AD9854 permits precise, internally generated linear or
externally programmed nonlinear pulsed or continuous FM over
a user-defined frequency range, duration, frequency resolution and
sweep direction(s). A block diagram of the FM chirp components
is shown in Figure 44.
48-BIT DELTA-
010 (RAMPED FSK)
FREQUENCY
HOLD
WORD
ACCUMULATOR
F1
FREQUENCY
RAMP RATE
Figure 44. FM Chirp Components
CLOCK
20-BIT
CLR ACC1
FREQUENCY
TUNING
WORD 1
ADDER
ACCUMULATOR
PHASE
SYSTEM
CLOCK
AD9854
CLR ACC2
OUT