AD9854 Analog Devices, AD9854 Datasheet - Page 6

• Manufacturer Part Number: AD9854
• Description: CMOS 300 MHz Quadrature Complete-DDS
• Manufacturer: Analog Devices

Pin
No.
55
56
61
64
68
69
70
71
AD9854
Pin Name
DACBP
DAC R
PLL FILTER
DIFF CLK
ENABLE
REFCLKB
REFCLK
S/P SELECT
MASTER
RESET
SET
Function
Common Bypass Capacitor Connection for Both I and Q DACs. A 0.01 F chip cap from this pin to
AVDD improves harmonic distortion and SFDR slightly. No connect is permissible (slight SFDR
degradation).
Common Connection for Both I and Q DACs to Set the Full-Scale Output Current. R
Normal R
This pin provides the connection for the external zero compensation network of the REFCLK
Multiplier’s PLL loop filter. The zero compensation network consists of a 1.3 k resistor in series
with a 0.01 F capacitor. The other side of the network should be connected to AVDD as close as
possible to Pin 60. For optimum phase noise performance, the REFCLK Multiplier can be bypassed
by setting the “Bypass PLL” bit in control register 1E.
Differential REFCLK Enable. A high level of this pin enables the differential clock inputs, REFCLK
and REFCLKB (Pins 69 and 68 respectively). The minimum differential signal amplitude
required is 800 mV p-p. The centerpoint or common-mode range of the differential signal ranges
from 1.6 V to 1.9 V.
The Complementary (180 Degrees Out-of-Phase) Differential Clock Signal. User should tie this pin
high or low when single-ended clock mode is selected. Same signal levels as REFCLK.
Single-Ended Reference Clock Input or One of Two Differential Clock Signals. Normal 3.3 V CMOS
logic levels or 1 V p-p sine wave centered about 1.6 V.
Selects Between Serial Programming Mode (Logic LOW) and Parallel Programming Mode
(Logic High).
Initializes the serial/parallel programming bus to prepare for user programming; sets programming
registers to a “do-nothing” state defined by the default values seen in the Table V. Active on logic
high. Asserting MASTER RESET is essential for proper operation upon power-up.
SET
range is from 8 k (5 mA) to 2 k (20 mA).
–6–
SET
= 39.9/I
REV. 0
OUT
.