MAX146 Maxim, MAX146 Datasheet - Page 9

• Manufacturer Part Number: MAX146
• Description: +2.7Low-Power / 8-Channel / Serial 12-Bit ADCs
• Manufacturer: Maxim

The MAX146/MAX147 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 12-bit digital output. A flexible ser-
ial interface provides easy interface to microprocessors
(µPs). Figure 3 is a block diagram of the MAX146/
MAX147.
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH7, and IN- is switched to COM. In
differential mode, IN+ and IN- are selected from the fol-
lowing pairs: CH0/CH1, CH2/CH3, CH4/CH5, and
CH6/CH7. Configure the channels with Tables 2 and 3.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
acquisition interval spans three SCLK cycles and ends
Figure 3. Block Diagram
_______________Detailed Description
REFADJ
SHDN
SCLK
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
VREF
DIN
CS
12
11
18
19
17
10
1
2
5
6
7
8
9
3
4
*A 2.00 (MAX147)
REGISTER
ANALOG
INPUT
INPUT
SHIFT
MUX
REFERENCE
(MAX146)
+1.21V
_______________________________________________________________________________________
CONTROL
LOGIC
T/H
Pseudo-Differential Input
20k
A
+2.500V
IN
2.06*
CLOCK
12-BIT
CLOCK
ADC
SAR
REF
INT
OUT
MAX146
MAX147
REGISTER
OUTPUT
SHIFT
+2.7V, Low-Power, 8-Channel,
HOLD
20
14
13
15
16
DOUT
SSTRB
V
DGND
AGND
. The
DD
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on C
The conversion interval begins with the input multiplex-
er switching C
negative input (IN-). In single-ended mode, IN- is sim-
ply COM. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 12-bit resolution. This
action is equivalent to transferring a 16pF x [(V
(V
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of
conversion, the positive input connects back to IN+,
and C
Figure 4. Equivalent Input Circuit
IN
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
-)] charge from C
HOLD
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
HOLD
VREF
as a sample of the signal at IN+.
Serial 12-Bit ADCs
charges to the input signal.
INPUT
MUX
|
IN+ - IN-
HOLD
12-BIT CAPACITIVE DAC
C
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
SWITCH
–
C
16pF
from the positive input (IN+) to the
HOLD
TRACK
SWITCH
|
+
HOLD
is sampled. At the end of the
T/H
R
9k
IN
HOLD
ZERO
to the binary-weighted
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
COMPARATOR
Track/Hold
IN
+
) -
9