STK6001 Syntec Semiconductor, STK6001 Datasheet - Page 22

• Manufacturer Part Number: STK6001
• Description: Scaler
• Manufacturer: Syntec Semiconductor

The video output circuit does not start the output operation until the input circuit fills the internal
buffer to a considerable extent.
Set the Register to adjust the filling extent of internal buffer.
Recommendation:
If the real output video is different from the ideal output video, the panel display may be abnormal due
to the last horizontal period being short; however, we can make this problem decrease by setting the
input Hsync. mode (EnSyncH{0x08[0]} = 1). Additionally, we still may set Reg. Shown below to fully
release this bottleneck.
In the input Hsync. mode (EnSyncH{0x08[0]} = 1), the output horizontal timing is synchronized with
the input Hsync. signal when EnFreeBlank = 0,the output Hsync. signal, during the output vertically
visible and blanking period, is set by PHS1 and PHS2,and PHT is abandoned. In the output vertically
blanking period, the output Hsync. signal is set by PHSB and PHT. When EnFreeBlank=1,the output
Hsync. signal, during the output vertically visible period, is set by PHS1 and PHS2.In the output
vertically blanking period, the output horizontal timing isn’t synchronized with the input Hsync. signal;
the output Hsync. signal is set by PHSB and PHT.
2.2.3 Buffer-less Timing Description
DlyLine[1:0]
DlyPxl[5:0]
PHSB[10:0]
EnFreeBlank
Input Video
Input Video
Output DE
Output DE
VCLK
VSI
HSI
{0x07}
{0x07}
{0x2F, 0x2E}
{0x08[2]}
DlyPxl x 4 VCLK
STK96C100
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DlyLine
Start output from this point
First DE