WM8253SCDS/V Wolfson Microelectronics Ltd., WM8253SCDS/V Datasheet - Page 17

• Manufacturer Part Number: WM8253SCDS/V
• Description: Specifications: Manufacturer: Wolfson Microelectronics ; Product Category: ADC (A/D Converters) ; RoHS: Details ; Number of Converters: 1 ; Number of ADC Inputs: 1 ; Conversion Rate: 6 MSPs ; Resolution: 16 bit ; Input Type: Voltage ; Interface
• Manufacturer: Wolfson Microelectronics Ltd.

WM8253
PROGRAMMABLE VSMP DETECT CIRCUIT
Figure 13 Internal VSMP Pulses Generated by Programmable VSMP Detect Circuit
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(VDEL = 000) INTVSMP
(VDEL = 001) INTVSMP
(VDEL = 010) INTVSMP
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
(VDEL = 101) INTVSMP
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP
(VDEL = 000) INTVSMP
(VDEL = 001) INTVSMP
(VDEL = 010) INTVSMP
(VDEL = 011) INTVSMP
(VDEL = 100) INTVSMP
(VDEL = 101) INTVSMP
(VDEL = 110) INTVSMP
(VDEL = 111) INTVSMP
INPUT
PINS
POSNNEG = 0
POSNNEG = 1
MCLK
VSMP
The VSMP input is used to determine the sampling point and frequency of the WM8253. Under
normal operation a pulse of 1 MCLK period should be applied to VSMP at the desired sampling
frequency (as shown in the Operating Mode Timing Diagrams) and the input sample will be taken on
the first rising MCLK edge after VSMP has gone low. However, in certain applications such a signal
may not be readily available. The programmable VSMP detect circuit in the WM8253 allows the
sampling point to be derived from any signal of the correct frequency, such as a CCD shift register
clock, when applied to the VSMP pin.
When enabled, by setting the VSMPDET control bit, the circuit detects either a rising or falling edge
(determined by POSNNEG control bit) on the VSMP input pin and generates an internal VSMP pulse.
This pulse can optionally be delayed by a number of MCLK periods, specified by the VDEL[2:0] bits.
Figure 13 shows the internal VSMP pulses that can be generated by this circuit for a typical clock
input signal. The internal VSMP pulse is then applied to the timing control block in place of the normal
VSMP pulse provided from the input pin. The sampling point then occurs on the first rising MCLK
edge after this internal VSMP pulse, as shown in the Operating Mode Timing Diagrams.
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PD, Rev 4.1, August 2011
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Production Data
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