WM8580AGEFT Wolfson Microelectronics Ltd., WM8580AGEFT Datasheet - Page 77

• Manufacturer Part Number: WM8580AGEFT
• Description: Multichannel Codec with S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics Ltd.

Production Data
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REGISTER
ADDRESS
CLKSEL
PLLB 1
PLLB 2
PLLB 3
PLLB 4
04h
05h
06h
07h
08h
R4
R5
R6
R7
R8
BIT
8:0
8:0
3:0
7:4
4:3
6:5
8:7
1:0
3:2
0
1
POSTSCALE_B
FREQMODE_B
MCLKOUTSRC
PLLB_K[21:18]
PRESCALE_B
DAC_CLKSEL
ADC_CLKSEL
PLLB_K[17:9]
CLKOUTSRC
PLLB_N[3:0]
PLLB_K[8:0]
LABEL
[1:0]
100100001
101111110
DEFAULT
1101
0111
10
00
11
00
00
0
0
Fractional (K) part of PLLB frequency ratio (R).
Value K is one 22-digit binary number spread over registers R4,
R5 and R6 as shown.
Note: PLLB_K must be set to specific values when the S/PDIF
receiver is used. Refer to S/PDIF Receive Mode Clocking
section for details.
Integer (N) part of PLLB frequency ratio (R).
Use values in the range 5 ≤ PLLB_N ≤ 13 as close as possible to
8
Note: PLLB_N must be set to specific values when the S/PDIF
receiver is used. Refer to S/PDIF Receive Mode Clocking
section for details.
PLL Pre-scale Divider Select
0 = Divide by 1 (PLL input clock = oscillator clock)
1 = Divide by 2 (PLL input clock = oscillator clock ÷ 2)
Note: PRESCALE_A must be set to the same value as
PRESCALE_B in PLL S/PDIF receiver mode.
PLL Post-scale Divider Select
PLL S/PDIF Receiver Mode
POSTSCALE_A is used to configure a 256fs or 128fs PLLACLK,
POSTSCALE_B is not used. Refer to Table 45.
PLL User Mode
Used in conjunction with the FREQMODE_x bits. Refer to Table
44.
PLL Output Divider Select
PLL S/PDIF Receiver Mode
FREQMODE_A is automatically controlled. FREQMODE_B is not
used.
PLL User Mode
Used in conjunction with the POSTSCALE_x bits. Refer to Table
44.
MCLK pin output source
CLKOUT pin source
DAC clock source
ADC clock source
00 = Input – Source MCLK pin
01 = Output – Source PLLACLK
10 = Output – Source PLLBCLK
11 = Output – Source OSCCLK
00 = No Output (tristate)
01 = Output – Source PLLACLK
10 = Output – Source PLLBCLK
11 = Output – Source OSCCLK
00 = MCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
00 = ADCMLCK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
DESCRIPTION
PD Rev 4.3 August 2007
WM8580
77