WM8940 Wolfson Microelectronics Ltd., WM8940 Datasheet - Page 59

• Manufacturer Part Number: WM8940
• Description: Mono Codec with Speaker Driver
• Manufacturer: Wolfson Microelectronics Ltd.

Pre-Production
w
GENERAL PURPOSE INPUT/OUTPUT
CONTROL INTERFACE
In 2-wire mode, the CSB pin is not required and it can be used as a GPIO pin. In 3 wire mode,
the MODE / GPIO can be configured as a GPIO by setting the MODE_GPIO register bit
Whichever pin is used for GPIO, it is controlled from the GPIO control register R8. The GPIOSEL bits
allow the chosen pin to be configured to perform a variety of useful tasks as shown in Table 57.
Note that SLOWCLKEN must be enabled when using the jack detect function.
Table 52 CSB/GPIO Control
SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS
Table 53 Control Interface Mode Selection
USE OF MODE AS A GPIO PIN IN 3-WIRE MODE
The control interface can operate as either a 3-wire or 2-wire interface. The MODE pin determines
the 2 or 3 wire mode as shown in Table 57.
The WM8940 is controlled by writing to registers through a serial control interface. A control word
consists of 24 bits. The first 7 bits (B23 to B16) are address bits that select which control register is
accessed. The remaining 16 bits (B15 to B0) are register bits, corresponding to the 16 bits in each
control register.
In 3-wire mode, MODE can be used as a GPIO pin. If MODE is being used as a GPIO output, the
partner device doesn’t have to drive MDE - the pin will be pulled-up internally causing 3-wire mode
will be selected. The GPIO function is enabled by setting the MODE_GPIO register bit. The MODE
pin can then be controlled using the GPIO register bits as described in <Table 39> [add as x-
reference].
To use MODE as a GPIO input, MODE must be undriven or driven high at start-up. Specifically
MODE must be high or hi-Z during an initial write to the control interface which sets the
MODE_GPIO register bit. After MODE_GPIO has been set, 3-wire mode selection is overridden
internally and the MODE pin can be used freely as a GPIO input or output.
R8
GPIO
control
REGISTER
ADDRESS
MODE
High
Hi-Z
Low
5:4
3
2:0
BIT
OPCLKDIV
GPIOPOL
GPIOSEL
LABEL
INTERFACE FORMAT
2 wire
3 wire
3 wire
00
0
000
DEFAULT
PLL Output clock division ratio
00=divide by 1
01=divide by 2
10=divide by 3
11=divide by 4
GPIO Polarity invert
0=Non inverted
1=Inverted
CSB/GPIO pin function select:
000=CSB input
001= Jack insert detect
010=Temp ok
011=Amute active
100=SYSCLK clock o/p
101=PLL lock
110=Reserved
111=Reserved
Pre-Production, Rev 3.0, February 2007
DESCRIPTION
WM8940
59