E6435BHFT Semtech Corporation, E6435BHFT Datasheet - Page 10

• Manufacturer Part Number: E6435BHFT
• Description: Per-pin Electronics Companion DAC
• Manufacturer: Semtech Corporation

RESET*
RESET* low resets the input shift register (no CLKIN
required), the central register, and input registers. With
RESET* high, the following leading edge of CLKIN will cause
reset condition to be removed (see Figure 21). Two clock
cycles are required after RESET* is set to logic “high” for
the DAC outputs to be enabled.
Programming Sequence
The DACs are programmed serially (see Figures 1 and 6).
On each rising edge of CLKIN, SDIN is loaded into a shift
register. It requires 24 Clocks to fully load the shift register.
LOAD
Following the serial input of a new DAC value, then LOAD
high for the leading edge of CLKIN loads the new DAC
value and its address into the Central Register. Following
the loading of the Central Register, LOAD needs to go low
followed by a leading edge of CLKIN so as to enable the
address decoder (see Figure 6).
STORE
Following the LOAD of the Central Register and the enabling
of the address docoder, the channel or set of channels
addressed DACs input register or channel function is
“stored” by a CLKIN with STORE high. Only upon the STORE
of a DAC or set of DAC’s “value latch” (Figure 2) does the
Edge6435/6436 compute the input to DAC’s Latch A (of
Rank A). There needs to be at least one clock edge after
LOAD is set to logic “low” before STORE is set to logic
“high” (see Figure 21).
TEST AND MEASUREMENT PRODUCTS
Circuit Description (continued)
Circuit Description (continued)
2006 Semtech Corp. / Rev. 3, 8/25/06
10
UPDATE
Following the STORE of multiple DAC values into Rank A
DAC latches, Rank B latches may be updated in parallel
with the values of their Rank A DAC latches by a CLKIN
with UPDATE high. There must be at least 16 clock cycles
between when STORE is set to logic “low” and UPDATE is
latched to logic “high” in order to latch the latest data
(see Figure 21).
RANK Selection
Referring to Figures 1, 2 and 3:
DACEN
DACEN low forces all DAC voltage outputs to ~0V and all
current outputs to ~0 mA (no CLKIN required). With
DACEN high, then a following leading edge of CLKIN will
cause DACs to be enabled (see Figure 23).
TEST MODE/SHIFTOUT*
TEST_MODE is used to enable the LDOUT and DACOUT
channels. Once enabled (TESTMODE = 1), SHIFTOUT*
can be used to begin transmission of serial data through
the LDOUT pin, or DAC outputs can be monitored at the
DACOUT pin (see Figure 24) (TEST_MODE functionality
does not depend on CLKIN)).
When addressing DAC channels that have been assigned
to a PinCast “set”, TEST-MODE is internally disabled in
order to prevent multiple DAC outputs from being
connected in parallel and possibly damaging the E6435/
6436.
RANK low selects Rank A latches to the DACs
(no CLKIN required).
RANK high selects Rank B latches to the DACs
(no CLKIN required).
Edge6435/6436
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