ADC574 Burr-Brown Corporation, ADC574 Datasheet - Page 9

• Manufacturer Part Number: ADC574
• Description: Microprocessor-compatible Analog-to-digital Converter
• Manufacturer: Burr-Brown Corporation

TABLE V. Timing Specifications.
FIGURE 6. Conversion Cycle Timing.
READING OUTPUT DATA
After conversion is initiated, the output data buffers remain
in a high-impedance state until the following four logic
conditions are simultaneously met: R/C high, STATUS low,
CE high, and CS low. Upon satisfaction of these conditions
the data lines are enabled according to the state of inputs
12/8 and A
ships and specifications.
In most applications the 12/8 input will be hard-wired in
either the high or low condition, although it is fully TTL-
and CMOS-compatible and may be actively driven if
DB11–
DB0
NOTE: Specifications are at +25 C and measured at 50% level of transitions.
STS
R/C
CE
CS
A
O
Convert Mode
Read Mode
SYMBOL
t
SAC
t
t
SSC
SRC
t
t
t
t
t
t
t
t
t
t
t
t
t
t
HRC
t
t
HRR
t
DSC
HEC
SSC
HSC
SRC
SAC
HAC
t
SSR
SRR
SAR
HSR
HAR
t
DD
HD
HS
O
HL
C
. See Figure 7 and Table V for timing relation-
t
DSC
t
t
t
HSC
HRC
HAC
High Impedance
t
HEC
STS Delay from CE
CE Pulse Width
CS to CE Setup time
CS low during CE high
R/C to CE setup
R/C low during CE high
A
A
Conversion time, 12-bit cycle
Access time from CE
Data valid after CE low
Output float delay
CS to CE setup
R/C to CE setup
A
CS valid after CE low
R/C high after CE low
A
STS delay after data valid
O
O
O
O
to CE setup
valid during CE high
valid after CE low
to CE setup
t
C
PARAMETER
8-bit cycle
9
FIGURE 7. Read Cycle Timing.
desired. When 12/8 is high, all 12 output lines (DB0–DB11)
are enabled simultaneously for full data word transfer to a
12-bit or 16-bit bus. In this situation the A
When 12/8 is low, the data is presented in the form of two
8-bit bytes, with selection of the byte of interest accom-
plished by the state of A
of the ADC574A to an 8-bit bus for transfer of left-justified
data is illustrated in Figure 8. The A
by the least significant bit of the address bus, allowing
storage of the output data word in two consecutive memory
locations.
DB11–
DB0
STS
R/C
CE
CS
A
O
MIN
300
50
50
50
50
50
50
15
10
25
50
50
50
0
0
0
0
t
t
t
SSR
SRR
SAR
TYP
100
400
60
30
20
20
20
20
20
13
75
35
25
High-Z
0
0
O
t
DD
during the read cycle. Connection
ADC574A
t
HS
O
MAX
1000
200
150
150
input is usually driven
Data Valid
25
17
t
t
t
HSR
HRR
HAR
O
state is ignored.
t
HL
t
HD
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
®