MAX8759 Maxim Integrated Products, MAX8759 Datasheet - Page 21

• Manufacturer Part Number: MAX8759
• Description: CCFL Backlight Controller
• Manufacturer: Maxim Integrated Products

Figure 9. SMBus Write Timing
and an ALS high-limit register (0x06). The MAX8759
only acknowledges these seven registers.
Communication starts with the master signaling the
beginning of a transmission with a START condition,
which is a high-to-low transition on SDA while SCL is
high. When the master has finished communicating
with the slave, the master issues a STOP condition,
which is a low-to-high transition on SDA while SCL is
high. The bus is then free for another transmission.
Figures 9 and 10 show the timing diagrams for signals
on the 2-wire interface. The address byte, command
byte, and data byte are transmitted between the START
and STOP conditions. The SDA state is allowed to
change only while SCL is low, except for the START
and STOP conditions. Data is transmitted in 8-bit words
and is sampled on the rising edge of SCL. Nine clock
cycles are required to transfer each byte in or out of the
MAX8759 since either the master or the slave acknowl-
edges the receipt of the correct byte during the ninth
clock. If the MAX8759 receives its correct slave
SMBCLK
SMBDATA
A = START CONDITION.
B = MSB OF ADDRESS CLOCKED INTO SLAVE.
C = LSB OF ADDRESS CLOCKED INTO SLAVE.
D = R/W BIT CLOCKED INTO SLAVE.
E = SLAVE PULLS SMBDATA LINE LOW .
Low-Cost, SMBus, CCFL Backlight Controller
t
SU:STA
A
t
HD:STA
______________________________________________________________________________________
t
LOW
B
t
HIGH
t
SU:DAT
C
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER.
G = MSB OF DATA CLOCKED INTO SLAVE.
H = LSB OF DATA CLOCKED INTO SLAVE.
I = SLAVE PULLS SMBDATA LINE LOW.
t
HD:DAT
D
E
F
address followed by R/W = 0, it expects to receive 1 or
2 bytes of information (depending on the protocol). If
the device detects a START or STOP condition prior to
clocking in the bytes of data, it considers this an error
condition and disregards all the data. If the transmis-
sion is completed correctly, the registers are updated
immediately after a STOP (or RESTART) condition. If
the MAX8759 receives its correct slave address fol-
lowed by R/W = 1, it expects to clock out the register
data selected by the previous command byte.
All MAX8759 registers are byte wide and accessible
through the read/write byte protocols mentioned in the
previous section. Their bit assignments are provided in
the following sections with reserved bits containing a
default value of zero.
Table 3 summarizes the register assignments, as well
as each register’s POR state. During shutdown, the ser-
ial interface remains fully functional.
t
HD:DAT
G
H
SMBus Register Definitions
J = ACKNOWLEDGE CLOCKED INTO MASTER.
K = ACKNOWLEDGE CLOCK PULSE.
L = STOP CONDITION, DATA EXECUTED BY SLAVE.
M = NEW START CONDITION .
I
J
K
t
SU:STO
L
t
BUF
M
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