16C6N5 Renesas Technology / Hitachi Semiconductor, 16C6N5 Datasheet - Page 39

• Manufacturer Part Number: 16C6N5
• Description: Renesas MCU
• Manufacturer: Renesas Technology / Hitachi Semiconductor

M16C/6N Group (M16C/6N5)
Rev.2.40
REJ03B0004-0240
Under development
This document is under development and its contents are subject to change.
Switching Characteristics
(Referenced to VCC = 5 V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 5.25 Memory Expansion Mode and Microprocessor Mode
NOTES:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
h(RD-CS)
h(WR-CS)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
h(BCLK-DB)
d(DB-WR)
h(WR-DB)
d(BCLK-HLDA)
d(BCLK-ALE)
h(BCLK-ALE)
d(AD-ALE)
h(ALE-AD)
d(AD-RD)
d(AD-WR)
dZ(RD-AD)
Symbol
1. Calculated according to the BCLK frequency as follows:
2. Calculated according to the BCLK frequency as follows:
3. Calculated according to the BCLK frequency as follows:
4. Calculated according to the BCLK frequency as follows:
Aug 25, 2006
0.5 ✕ 10
f(BCLK)
(n –0.5) ✕ 10
0.5 ✕ 10
f(BCLK)
0.5 ✕ 10
f(BCLK)
f(BCLK)
Address output delay time
Address output hold time (in relation to BCLK)
Address output hold time (in relation to RD)
Address output hold time (in relation to WR)
Chip select output delay time
Chip select output hold time (in relation to BCLK)
Chip select output hold time (in relation to RD)
Chip select output hold time (in relation to WR)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (in relation to BCLK)
Data output hold time (in relation to BCLK)
Data output delay time (in relation to WR)
Data output hold time (in relation to WR)
__________
HLDA output delay time
ALE signal output delay time (in relation to BCLK)
ALE signal output hold time (in relation to BCLK)
ALE signal output delay time (in relation to Address)
ALE signal output hold time (in relation to Address)
RD signal output delay from the end of Address
WR signal output delay from the end of Address
Address output floating start time
(for 2- to 3-wait setting, external area access and multiplexed bus selection)
9
9
9
– 10 [ns]
– 25 [ns]
– 15 [ns]
page 39 of 84
9
– 40 [ns]
Parameter
n is “2” for 2-wait setting, “3” for 3-wait setting.
Figure 5.2
Measuring
Condition
5. Electric Characteristics (T/V-ver.)
(NOTE 1)
(NOTE 1)
(NOTE 1)
(NOTE 1)
(NOTE 2)
(NOTE 1)
(NOTE 3)
(NOTE 4)
Min.
–4
4
4
0
0
4
0
0
Standard
Max.
VCC = 5 V
25
25
25
25
40
40
15
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns