ADS7805 Burr-Brown Corporation, ADS7805 Datasheet - Page 8

• Manufacturer Part Number: ADS7805
• Description: 16-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

READING DATA
The ADS7805 outputs full or byte-reading parallel data in
Binary Two’s Complement data output format. The parallel
output will be active when R/C (pin 24) is HIGH and CS
(pin 25) is LOW. Any other combination of CS and R/C will
tri-state the parallel output. Valid conversion data can be
read in a full parallel, 16-bit word or two 8-bit bytes on pins
6-13 and pins 15-22. BYTE (pin 23) can be toggled to read
both bytes within one conversion cycle. Refer to Table III
for ideal output codes and Figure 2 for bit locations relative
to the state of BYTE.
Table III. Ideal Input Voltages and Output Codes.
PARALLEL OUTPUT (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 26) will go HIGH. Valid data
from conversion ‘n’ will be available on D15-D0 (pin 6-13
and 15-22). BUSY going HIGH can be used to latch the
data. Refer to Table IV and Figures 3 and 5 for timing
specifications.
FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).
DESCRIPTION
Full Scale Range
Least Significant
Bit (LSB)
+Full Scale
(10V – 1LSB)
Midscale
One LSB below
Midscale
–Full Scale
®
ANALOG INPUT
ADS7805
9.999695V
Bit 15 (MSB)
–305 V
305 V
–10V
10V
0V
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
10
11
12
13
14
6
7
8
9
0111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000
BINARY TWO’S COMPLEMENT
BINARY CODE
BYTE LOW
ADS7805
DIGITAL OUTPUT
23
22
21
20
19
18
17
16
15
HEX CODE
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
FFFF
7FFF
0000
8000
8
Bit 0 (LSB)
PARALLEL OUTPUT (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 7 s after
the start of conversion ‘n’. Do not attempt to read data from
7 s after the start of conversion ‘n’ until BUSY (pin 26)
goes HIGH; this may result in reading invalid data. Refer to
Table IV and Figures 3 and 5 for timing specifications.
Note! For the best possible performance, data should not be
read during a conversion. The switching noise of the asyn-
chronous data transfer can cause digital feedthrough degrad-
ing the converter’s performance.
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate
the output mode of the converter. See Figure 3.
TABLE IV. Conversion Timing.
SYMBOL
t
7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
t
t
t
t
t
t
t
t
t
t
t
t
t
t
+ t
10
11
12
13
14
1
2
3
4
5
6
7
8
9
6
10
11
12
13
14
6
7
8
9
Data Valid Delay after R/C LOW
BUSY Delay after Data Valid
BYTE HIGH
BUSY Delay from R/C LOW
Time Between Conversions
R/C to CS Setup Time
Bus Relinquish Time
ADS7805
Convert Pulse Width
Previous Data Valid
End of Conversion
BUSY Delay after
Throughput Time
Bus Access Time
Conversion Time
Acquisition Time
and BYTE Delay
DESCRIPTION
Aperture Delay
after R/C LOW
BUSY LOW
23
22
21
20
19
18
17
16
15
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15 (MSB)
+5V
MIN TYP MAX UNITS
40
10
50
10
10
10
220
200
7.6
7.4
40
35
9
7000
65
83
10
83
8
8
8
2
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s