ADS7835E Burr-Brown Corporation, ADS7835E Datasheet - Page 12

• Manufacturer Part Number: ADS7835E
• Description: 12-Bit/ High-Speed/ Low Power Sampling ANALOG-TO-DIGITAL CONVERTER
• Manufacturer: Burr-Brown Corporation

TABLE III. Ideal Input Voltages and Output Codes.
FIGURE 7. Typical DSP Interface Timing.
logic.
DATA FORMAT
The ADS7835 output data is in Binary Two’s Complement
format as shown in Table III. This table shows the ideal
output code for the given input voltage and does not include
NOTES: (1) –2.5V to +2.5V when the internal reference is used. (2) 1.22mV
with a 2.5V reference.
the effects of offset, gain, or noise.
DSP INTERFACING
FIGURE 8. Typical SPI/QSPI Interface Timing.
DESCRIPTION
Full-Scale Input
Least Significant Bit
+Full Scale
Mid-Scale
Mid-Scale –1LSB
–Full Scale
Range
CONV
(LSB)
DATA
CONV
CLK
DATA
CLK
(2)
15
®
ADS7835
(–V
16
1
ANALOG INPUT
–V
REF
t
REF
–0.00122V
–2.49878V
DRP
2.49878V
to +V
to +V
0V
1
2
REF
REF
(MSB)
)/4096
(MSB)
D11
D11
(1)
3
2
0111 1111 1111
0000 0000 0000
1111 1111 1111
1000 0000 0000
D10
D10
DIGITAL OUTPUT
BINARY
BINARY TWO’S
COMPLEMENT
4
3
CODE
CODE
HEX
7FF
FFF
000
800
D1
D1
12
13
12
(LSB)
(LSB)
D0
D0
14
13
Figure 7 shows a timing diagram that might be used with a
typical digital signal processor such as a TI DSP. For the
Buffered Serial Port (BSP) on the TMS320C54X family,
CONV would tied to BFSX, CLK would be tied to BCLKX,
and DATA would be tied to BDR.
SPI/QSPI INTERFACING
Figure 8 shows the timing diagram for a typical Serial
Peripheral Interface (SPI) or Queued Serial Peripheral Inter-
face (QSPI). Such interfaces are found on a number of
microcontrollers from various manufacturers. CONV would
be tied to a general purpose I/O pin (SPI) or to a PCX pin
(QSPI), CLK would be tied to the serial clock, and DATA
would be tied to the serial input data pin such as MISO
(Master In Slave Out).
Note the time t
maximum amount of time between CONV going LOW and
the start of the conversion clock. Since CONV going LOW
places the S/H in the hold mode and because the hold
capacitor loses charge over time, there is a requirement that
time t
DRP
15
14
be met as well as the maximum clock period
16
15
DRP
shown in Figure 8. This represents the
16
1
(MSB)
D11
2
1
t
ACQ
D10
2
3
(MSB)
D11
D9
4
3