ADSP-21060 Analog Devices, ADSP-21060 Datasheet - Page 2

• Manufacturer Part Number: ADSP-21060
• Description: ADSP-2106x SHARC DSP Microcomputer Family
• Manufacturer: Analog Devices

TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 3
ADSP-21000 FAMILY CORE ARCHITECTURE . . . . . . . 3
ADSP-21060/ADSP-21060L FEATURES . . . . . . . . . . . . . . 4
DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 8
TARGET BOARD CONNECTOR FOR EZ-ICE
RECOMMENDED OPERATING CONDITIONS (5 V) . 13
ELECTRICAL CHARACTERISTICS (5 V) . . . . . . . . . . . 13
POWER DISSIPATION ADSP-21060 (5 V) . . . . . . . . . . . . 14
RECOMMENDED OPERATING CONDITIONS (3.3 V) 15
ELECTRICAL CHARACTERISTICS (3.3 V) . . . . . . . . . . 15
POWER DISSIPATION ADSP-21060L (3.3 V) . . . . . . . . . 16
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 17
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 17
OUTPUT DRIVE CURRENTS . . . . . . . . . . . . . . . . . . . . . 39
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 42
240-LEAD MQFP PIN CONFIGURATIONS . . . . . . . . . . 43
PACKAGE DIMENSIONS (240-Lead MQFP) . . . . . . . . . 44
225-Ball Plastic Ball Grid Array (PBGA)
PACKAGE DIMENSIONS (225-Ball Grid Array PBGA) . . . 47
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
FIGURES
Figure 1. ADSP-21060/ADSP-21060L Block Diagram . . . . 1
Figure 2. ADSP-2106x System . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Shared Memory Multiprocessing System . . . . . . . . 6
Figure 4. ADSP-21060/ADSP-21060L Memory Map . . . . . 7
Figure 5. Target Board Connector For ADSP-2106x
EZ-ICE is a registered trademark of Analog Devices, Inc.
ADSP-21060/ADSP-21060L
PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Memory Read—Bus Master . . . . . . . . . . . . . . . . . . . . . . . 20
Memory Write—Bus Master . . . . . . . . . . . . . . . . . . . . . . 21
Synchronous Read/Write—Bus Master . . . . . . . . . . . . . . 22
Synchronous Read/Write—Bus Slave . . . . . . . . . . . . . . . . 24
Multiprocessor Bus Request and Host Bus Request . . . . . 25
Asynchronous Read/Write—Host to ADSP-2106x . . . . . . 27
Three-State Timing—Bus Master, Bus Slave,
DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Link Ports: 1 × CLK Speed Operation . . . . . . . . . . . . . . 32
Link Ports: 2 × CLK Speed Operation . . . . . . . . . . . . . . 33
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
JTAG Test Access Port and Emulation . . . . . . . . . . . . . . . 38
Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45, 46
EZ-ICE Emulator (Jumpers in Place) . . . . . . . . . . . . . . . 11
HBR, SBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
®
Figure 6. JTAG Scan Path Connections for Multiple
Figure 7. JTAG Clocktree for Multiple ADSP-2106x
Figure 8. Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Memory Read—Bus Master . . . . . . . . . . . . . . . . 20
Figure 14. Memory Write—Bus Master . . . . . . . . . . . . . . . 21
Figure 15. Synchronous Read/Write—Bus Master . . . . . . . 23
Figure 16. Synchronous Read/Write—Bus Slave . . . . . . . . . 24
Figure 17. Multiprocessor Bus Request and Host Bus
Figure 18a. Synchronous REDY Timing . . . . . . . . . . . . . . 27
Figure 18b. Asynchronous Read/Write—Host to
Figure 19a. Three-State Timing (Bus Transition Cycle,
Figure 19b. Three-State Timing (Host Transition Cycle) . . 29
Figure 20. DMA Handshake Timing . . . . . . . . . . . . . . . . . 31
Figure 21. Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 22. Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 23. External Late Frame Sync . . . . . . . . . . . . . . . . . 37
Figure 24. IEEE 11499.1 JTAG Test Access Port . . . . . . . 38
Figure 25. Output Enable/Disable . . . . . . . . . . . . . . . . . . . 40
Figure 26. Equivalent Device Loading for AC Measurements
Figure 27. Voltage Reference Levels for AC Measurements
Figure 28. ADSP-2106x Typical Drive Currents
Figure 29. Typical Output Rise Time (10%–90% V
Figure 30. Typical Output Rise Time (0.8 V–2.0 V)
Figure 31. Typical Output Delay or Hold vs. Load Capacitance
Figure 32. ADSP-2106x Typical Drive Currents
Figure 33. Typical Output Rise Time (10%–90% V
Figure 34. Typical Output Rise Time (0.8 V–2.0 V) vs. Load
Figure 35. Typical Output Delay or Hold vs. Load Capacitance
ADSP-2106x Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ADSP-2106x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SBTS Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
(Includes All Fixtures) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
(Except Output Enable/Disable) . . . . . . . . . . . . . . . . . . . 40
(V
vs. Load Capacitance (V
vs. Load Capacitance (V
(at Maximum Case Temperature) (V
(V
vs. Load Capacitance (V
Capacitance (V
(at Maximum Case Temperature) (V
DD
DD
= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DD
= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 42
DD
DD
DD
= 5 V) . . . . . . . . . . . . . . . . . . . 41
= 5 V) . . . . . . . . . . . . . . . . . . . 41
= 3.3 V) . . . . . . . . . . . . . . . . . 41
DD
DD
= 5 V) . . . . . . . . . 41
= 3.3 V) . . . . . . . . 42
DD
DD
)
)