AD8304 Analog Devices, AD8304 Datasheet - Page 12

• Manufacturer Part Number: AD8304
• Description: 160 DB Logarithmic Amplifier With Photo-diode Interface
• Manufacturer: Analog Devices

AD8304
Low Supply Slope and Intercept Adjustment
When using the device with a positive supply less than 4 V, it is
necessary to reduce the slope and intercept at the VLOG pin in
order to preserve good log conformance over the entire 160 dB
operating range. The voltage at the VLOG pin is generated by an
internal current source with an output current of 40 µA/decade
feeding the internal laser trimmed output resistance of 5 kΩ.
When the voltage at VLOG pin exceeds V
source ceases to respond linearly to logarithmic increases in
current. This headroom issue can be avoided by reducing the
logarithmic slope and intercept at the VLOG pin. This is accom-
plished by connecting an external resistor R
ground in combination with an intercept lowering resistor R
The values shown in Figure 6 illustrate a good solution for a
3.0 V positive supply. The resulting logarithmic slope measured
at VLOG is 62.5 mV/decade with a new intercept of 57 fA. The
original logarithmic slope of 200 mV/decade can be recovered
using voltage gain on the internal buffer amplifier.
NC = NO CONNECT
NC = NO CONNECT
R1
750
C1
1nF
10nF
R1
750
C1
1nF
I
10nF
PD
I
PD
NC
NC
4
6
3
5
4
6
3
5
VSUM
VSUM
VPDB
INPT
VPDB
VSUM
VSUM
INPT
VNEG
VNEG
VPS2
VPS2
1
1
PDB
PDB
10
10
PWDN
~10k
PWDN
~10k
ACOM
COMPENSATION
TEMPERATURE
BIAS
ACOM
COMPENSATION
TEMPERATURE
BIAS
2
2
14
14
0.5V
VPS1
0.5V
VPS1
VREF
VOUT
VREF
P
VOUT
S
12
5k
12
– 2.3 V, the current
5k
from the c pin to
11
11
BFNG
VLOG
VREF
BFNG
BFIN
BFIN
13
7
8
9
V
13
7
8
9
V
P
62.5mV/DEC
VREF
P
VLOG
RA
4.98k
RZ
15.4k
2.67k
RA
RS
Z
V
V
.
OUT
OUT
RC
RB
RB
2.26k
Using the Adaptive Bias
For most photodiode applications, the placement of the anode
somewhat above ground is acceptable, as long as the positive bias
on the cathode is adequate to support the peak current for a
particular diode, limited mainly by its series resistance. To address
this matter, the AD8304 provides for the diode a bias that varies
linearly with the current. This voltage appears at pin VPDB, and
varies from 0.6 V (reverse-biasing the diode by 0.1 V) for
I
I
0.1 V when the series resistance of the photodiode is 200 Ω. For
optical power measurements over a wide dynamic range the adaptive
biasing function will be valuable in minimizing dark current while
preventing the loss of photodiode bias at high currents. Use of the
adaptive bias feature is shown in Figure 7.
Capacitor CPB between the photodiode cathode at pin VPDB
and ground is included to lower the impedance at this node and
thereby improve the high frequency accuracy at those current
levels where the AD8304 bandwidth is high. It also ensures an
HF path for any high frequency modulation on the optical sig-
nal which might not otherwise be accurately averaged. It will not
be necessary in all cases, and experimentation may be required to
find an optimum value.
Changing the Voltage at the Summing Node
The default value of VSUM is determined by using a quarter of
VREF (2 V). This may be altered by applying an independent
voltage source to VSUM, or by adding an external resistive divider
from VREF to VSUM. This network will operate in parallel with
the internal divider (40 kΩ and 13.3 kΩ), and the choice of exter-
nal resistors should take this into account. In practice, the total
resistance of the added string may be as high as 10 kΩ (consum-
ing 400 mA from VREF). Low values of VSUM and thus V
(see Figure 13) are not advised when large values of I
expected.
Implementing Low-Pass Filters
Noise, leading to uncertainty in an observed value, is inherent to
all measurement systems. Translinear log amps exhibit significant
amounts of noise for reasons stated above, and are more trouble-
some at low current levels. The standard way of addressing this
problem is to average the measurement over an appropriate time
interval. This can be achieved in the digital domain, in post-ADC
DSP, or in analog form using a variety of low-pass structures.
PD
PD
R1
750
C1
1nF
CPB
10nF
= 10 mA. This results in a constant internal junction bias of
= 100 pA and rises to 2.6 V (for a diode bias of 1 V) at
I
VPDB
PD
4
6
3
5
VSUM
VSUM
INPT
VNEG
VPS2
1
PDB
10
PWDN
~10k
ACOM
COMPENSATION
TEMPERATURE
BIAS
2
14
0.5V
VPS1
VREF
VOUT
12
5k
11
VLOG
BFNG
BFIN
13
7
8
9
V
P
PD
VREF
RA
are
CFILT
CE
RB
V
OUT