MT58L128L18F Micron Semiconductor Products, Inc., MT58L128L18F Datasheet
MT58L128L18F
Available stocks
Related parts for MT58L128L18F
MT58L128L18F Summary of contents
Page 1
... Operating Temperature Range Commercial (0°C to +70°C) Part Number Example: MT58L64L36FT-8.5 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM ™ ...
Page 2
... CE2 CE2# OE# NOTE: Functional Block Diagrams illustrate simplified device operation. See truth table, pin descriptions and timing diagrams for detailed information. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 FLOW-THROUGH SYNCBURST SRAM FUNCTIONAL BLOCK DIAGRAM 128K ...
Page 3
... Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM Micron’s 2Mb SyncBurst SRAMs operate from a +3 ...
Page 4
... Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 FLOW-THROUGH SYNCBURST SRAM PIN ASSIGNMENT (Top View) 100-Pin TQFP ...
Page 5
... ADV ADSP# 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 FLOW-THROUGH SYNCBURST SRAM TYPE SA0 Input Synchronous Address Inputs: These inputs are registered and must SA1 meet the setup and hold times around the rising edge of CLK. ...
Page 6
... NC/SA 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 FLOW-THROUGH SYNCBURST SRAM TYPE Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW ...
Page 7
... WRITE All Bytes WRITE All Bytes NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM THIRD ADDRESS (INTERNAL) X...X01 X ...
Page 8
... ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 FLOW-THROUGH SYNCBURST SRAM ADSP# ADSC# ADV# WRITE# OE# USED ...
Page 9
... V Q should never exceed V DD 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 FLOW-THROUGH SYNCBURST SRAM *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional ...
Page 10
... Typical values are measured at 3.3V, 25°C, and 15ns cycle time. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 FLOW-THROUGH SYNCBURST SRAM = +3.3V +0.3V/-0.165V unless otherwise noted) CONDITIONS SYM or ≥ ...
Page 11
... DESCRIPTION Thermal Resistance Test conditions follow standard test methods (Junction to Ambient) Thermal Resistance (Junction to Top of Case) NOTE: 1. This parameter is sampled. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 FLOW-THROUGH SYNCBURST SRAM CONDITIONS SYMBOL T = 25° MHz 3.3V ...
Page 12
... Chip enable must be valid at each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 FLOW-THROUGH SYNCBURST SRAM -6.8 ...
Page 13
... The Micron 128K x 18, 64K x 32, and 64K x 36 SyncBurst SRAM timing is dependent upon the capaci- tive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 FLOW-THROUGH SYNCBURST SRAM 2.5V I/O AC TEST CONDITIONS = (V /2.2) + 1.5V Input pulse levels ............. V ...
Page 14
... I ISB2Z ALL INPUTS (except ZZ) Outputs (Q) 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM The ZZ pin is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic HIGH, I ...
Page 15
... CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. 4. Outputs are disabled t KQHZ after deselect. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 FLOW-THROUGH SYNCBURST SRAM READ TIMING t ADSS t ADSH A2 ...
Page 16
... Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for the x18 version; or GW# HIGH and BWE#, BWa#-BWd# LOW for the x32 and x36 versions. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 FLOW-THROUGH SYNCBURST SRAM WRITE TIMING ...
Page 17
... The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 FLOW-THROUGH SYNCBURST SRAM READ/WRITE TIMING A3 A4 ...
Page 18
... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, SyncBurst, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 FLOW-THROUGH SYNCBURST SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) 0.625 14.00 ± ...
Page 19
... Changed heading on Mechanical Drawing from BGA to FBGA Added 165-Pin FBGA package, REV 3/00, FINAL ....................................................................................... May/23/00 Added PRELIMINARY PACKAGE DATA to diagram 2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM MT58L128L18F_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...