MT58L128L18F Micron Semiconductor Products, Inc., MT58L128L18F Datasheet - Page 16

• Manufacturer Part Number: MT58L128L18F
• Description: 2Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

NOT RECOMENDED FOR NEW DESIGNS
WRITE TIMING PARAMETERS
NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.
2Mb: 128K x 18, 64K x 32/36 Flow-Through SyncBurst SRAM
MT58L128L18F_C.p65 – Rev. C, Pub. 11/02
BWa#-BWd#
SYMBOL
t
f
t
t
t
t
t
t
t
KC
KF
KH
KL
OEHZ
AS
ADSS
AAS
WS
ADDRESS
(NOTE 2)
ADSC#
ADSP#
BWE#,
ADV#
GW#
OE#
CLK
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for the x18 version;
CE#
Q
D
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
output data contention for the time period prior to the byte write enable inputs being sampled.
or GW# HIGH and BWE#, BWa#-BWd# LOW for the x32 and x36 versions.
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
8.0
1.8
1.8
1.8
1.8
1.8
1.8
-6.8
BURST READ
125
3.8
High-Z
t ADSS
8.8
1.9
1.9
2.0
2.0
2.0
2.0
t CES
t AS
A1
-7.5
t ADSH
t CEH
t AH
t KH
t OEHZ
(NOTE 3)
113
4.2
BYTE WRITE signals are
ignored when ADSP# is LOW.
t KC
t ADSS
t KL
Single WRITE
t DS
10.0
D(A1)
1.9
1.9
2.0
2.0
2.0
2.0
t ADSH
-8.5
t DH
100
5.0
A2
4.0
4.0
2.5
2.5
2.5
2.5
15
(NOTE 4)
-10
5.0
D(A2)
66
(NOTE 5)
WRITE TIMING
MHz
ns
ns
ns
ns
ns
ns
ns
ns
D(A2 + 1)
(NOTE 1)
t WS
BURST WRITE
16
FLOW-THROUGH SYNCBURST SRAM
t WH
D(A2 + 1)
SYMBOL
t
t
t
t
t
t
t
t
DS
CES
AH
ADSH
AAH
WH
DH
CEH
ADV# suspends burst.
2Mb: 128K x 18, 64K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D(A2 + 2)
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1.8
1.8
0.5
0.5
0.5
0.5
0.5
0.5
-6.8
ADSC# extends burst.
D(A2 + 3)
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
-7.5
t ADSS
A3
D(A3)
t ADSH
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
DONÕT CARE
-8.5
Extended BURST WRITE
t AAS
t WS
D(A3 + 1)
t AAH
t WH
©2002, Micron Technology, Inc.
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
-10
UNDEFINED
D(A3 + 2)
ns
ns
ns
ns
ns
ns
ns
ns