MT9042B Zarlink Semiconductor, MT9042B Datasheet

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MT9042B

Manufacturer Part Number
MT9042B
Description
Manufacturer
Zarlink Semiconductor
Datasheet

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Features
Applications
Meets jitter requirements for AT&T TR62411
Stratum 3, 4 and Stratum 4 Enhanced for DS1
interfaces and for ETSI ETS 300 011 for E1
interfaces
Provides C1.5, C3, C2, C4, C8 and C16 output
clock signals
Provides 8kHz ST-BUS framing signals
Selectable 1.544MHz, 2.048MHz or 8kHz input
reference signals
Accepts reference inputs from two independent
sources
Provides bit error free reference switching -
meets phase slope and MTIE requirements
Operates in either Normal, Holdover and
Freerun modes
Synchronization and timing control for
multitrunk T1 and E1 systems
ST-BUS clock and frame pulse sources
Primary Trunk Rate Converters
OSCo
RSEL
LOS1
LOS2
OSCi
SEC
PRI
Reference
MS1
Master
Select
Clock
MUX
Reference
Select
Control State Machine
Automatic/Manual
MS2
Corrector
Selected
Refer-
Enable
ence
TIE
RST
Figure 1 - Functional Block Diagram
Corrector
Circuit
TRST
TIE
Select
State
Virtual
Refer-
ence
GTo
Guard Time
Impairment
Description
The MT9042B Multitrunk System Synchronizer
contains a digital phase-locked loop (DPLL), which
provides timing and synchronization signals for
multitrunk T1 and E1 primary rate transmission links.
The MT9042B generates ST-BUS clock and framing
signals that are phase locked to either a 2.048MHz,
1.544MHz, or 8kHz input reference.
The MT9042B is compliant with AT&T TR62411
Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300
011. It will meet the jitter tolerance, jitter transfer,
intrinsic
accuracy, capture range, phase slope and MTIE
requirements for these specifications.
Monitor
Circuit
DPLL
Input
Select
State
GTi
Multitrunk System Synchronizer
MT9042BP
VDD
jitter,
Feedback
VSS
Ordering Information
FS1
-40 C to +85 C
frequency
Frequency
Interface
Output
Circuit
Select
Preliminary Information
MUX
28 Pin PLCC
ISSUE 1
FS2
accuracy,
MT9042B
October 1996
holdover
C1.5o
C3o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
3-97

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MT9042B Summary of contents

Page 1

... The MT9042B generates ST-BUS clock and framing signals that are phase locked to either a 2.048MHz, 1.544MHz, or 8kHz input reference. The MT9042B is compliant with AT&T TR62411 Stratum 3, 4 and 4 Enhanced, and ETSI ETS 300 011. It will meet the jitter tolerance, jitter transfer, intrinsic accuracy, capture range, phase slope and MTIE requirements for these specifi ...

Page 2

Package Outlines Dim D General- (lead coplanarity) A Notes Not ...

Page 3

... Fax: +65 333 6192 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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