MT9122 Zarlink Semiconductor, MT9122 Datasheet
MT9122
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MT9122 Summary of contents
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... The MT9122 architecture contains two echo cancellers which can be configured to provide dual channel 64 millisecond echo cancellation or single channel 128 millisecond echo cancellation. The MT9122 supports ITU-T G.165 or G.164 tone disable requirements. The MT9122 Controller or Controllerless. Controller mode allows access to an array of features for customizing MT9122 operation ...
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... MT9122 1 ENA1 28 2 ENB1 27 ENA2 ENB2 25 5 Rin 24 PDIP Sin 6 23 VSS MCLK NLP 19 11 REV 18 LAW 12 17 FORMAT PWRDN Pin Description Pin # Name 1 ENA1 SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input). This pin has dual functions depending on whether SSI or ST-BUS is selected ...
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... An active low selects sign-magnitude PCM code. When high, selects ITU-T (G.711) PCM code. This control is for both echo cancellers and is valid for both controller and controllerless modes. 14 PWRDN Power-down (Input): An active low resets the device and puts the MT9122 into a low-power stand-by mode. 15 TD2 ...
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... CONFIG1/ Device Configuration Pins (Inputs). CONFIG2 When CONFIG1 and CONFIG2 pins are both logic 0, the MT9122 serial microport is enabled. This configuration is defined as Controller Mode. When CONFIG1 and CONFIG2 pins are in any other logic combination, the MT9122 is configured in Controllerless Mode. See Table 3. ...
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... Refer to Table 7 for a complete list. Controller mode is selected when CONFIG1 and CONFIG2 pins are both connected to Vss. Each echo canceller in the MT9122 has four functional states: Mute, Bypass, Disable Adaptation and Enable Adaptation. These are explained in the section entitled Echo Canceller Functional States. ...
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... After echo cancellation, there is always a small amount of residual echo which may still be audible. The MT9122 uses an NLP to remove residual echo signals which have a level lower than the Adaptive Suppression Threshold (TSUP in G.165). This threshold depends upon the level of the Rin (Lrin) ...
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... When the PHDis bit is set to 1, G.164 tone disable requirements are selected. This applies to all four Tone Detectors. In response to a valid disable tone, the MT9122 must be switched from the Enable Adaptation state to the Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors internally control the switching between Enable Adaptation and Bypass states ...
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... Register 1 and Control Register 2 through four control bits: MuteS, MuteR, Bypass and AdaptDis. See Register Summary for details. MT9122 Throughput Delay The throughput delay of the MT9122 varies according to the data path and the device configuration. For all device configurations, except Data Sheet ...
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... Power Down Forcing the PWRDN pin to logic low, will put the MT9122 into a power down state. In this state all internal clocks are halted, the DATA1, Sout and Rout pins are tristated and the F0od, TD1, and TD2 pins output high. ...
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... F0i pin. When a valid ST-BUS frame pulse is applied to the F0i pin, the MT9122 will assume ST-BUS operation. If F0i is tied continuously to Vss the MT9122 will assume SSI operation. ST-BUS Operation The ST-BUS PCM interface conforms to Zarlink’s ...
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... MT9122, by the Motorola processor, output data from the DATA1 pin must be ignored. This also means that input data on the DATA2 pin is ignored by the MT9122 during a valid read by the Motorola processor. All data transfers through the microport are two bytes long ...
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... Detector tion when narrow band signal is detected. Offset Null Filter Continuously enabled which removes the DC compo- nent in the PCM input. Table 7 - MT9122 Function Control Summary 12 Controllerless Set bits Extended-Delay to 0 and BBM Control Reg- ister 1 to select. Set bit BBM Control Register 1 to select. ...
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... ECA ECA MT9122 ECB ECB ...
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... MT9122 C4i F0i 0 F0od PORT1 Rin Sout PORT2 Sin Rout outputs=High impedance inputs = don’t care indicates that an input channel is bypassed to an output channel ST-BUS Mode 3 supports connection to 2B+D devices where timeslots 0 and 1 transport D and C channels and both echo canceller I/O channels are assigned to ST-BUS timeslots 2 and 3 ...
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... SCLK CS ➂ ➀ Delays due to internal processor timing which are transparent to the MT9122. ➁ The MT9122: latches receive data on the rising edge of SCLK outputs transmit data on the falling edge of SCLK ➂ The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high. ➃ ...
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... Transmit ➁ SCLK CS ➂ ➀ Delays due to internal processor timing which are transparent to the MT9122. ➁ The MT9122: latches receive data on the rising edge of SCLK outputs transmit data on the falling edge of SCLK ➂ The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high ...
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... HPFDis MuteS AutoTD NBDis MuteR Conv Down Active TDG MT9122 Power Reset Value 0000 0000 0 Power Reset Value 0 0000 0010 0 Power Reset Value 0000 0000 0 ADDRESS = 02h READ ADDRESS = 22h READ Power Reset Value 0000 0000 0 17 ...
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... MT9122 Echo Canceller A, Flat Delay Register Echo Canceller B, Flat Delay Register Echo Canceller A, Decay Step Number Register Echo Canceller B, Decay Step Number Register Echo Canceller A, Decay Step Size Control Register Echo Canceller B, Decay Step Size Control Register ...
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... MT9122 ADDRESS = 0Dh READ ADDRESS = 2Dh READ Power Reset Value N/A 8 ADDRESS = 0Ch READ ADDRESS = 2Ch READ Power Reset Value N/A 0 ADDRESS = 0Fh READ ADDRESS = 2Fh READ Power Reset Value N/A 8 ADDRESS = 0Eh READ ADDRESS = 2Eh READ ...
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... MT9122 Echo Canceller A, Double-Talk Detection Threshold Register 2 ADDRESS = 15h WRITE/READ VERIFY Echo Canceller B, Double-Talk Detection Threshold Register 2 ADDRESS = 35h WRITE/READ VERIFY DTDT DTDT DTDT DTDT Echo Canceller A, Double-Talk Detection Threshold Register 1 ADDRESS = 14h WRITE/READ VERIFY Echo Canceller B, Double-Talk Detection Threshold Register 1 ...
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... Clockin echo path MT9160 5V CODEC Dout T R Din Clockin F0i echo path MT8941 PLL F0 C4 Figure 13 - (Analog Trunk) Wireless Application Diagram MT9122 is in SSI mode MT9125 ADPCM MT9122 Sin Sout DSTi ADPCMo ADPCMi ENA EN1 ENB EN2 BCLK C20 Rout Rin ...
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... MT8910 2B1Q MT8972 Bi-phase MT8931 S-INT DSTo T R echo path C4o F0b Figure 15 - (Basic Rate ISDN) Wired Telephone Application Diagram 22 MT9122 connected in ST-BUS mode 1 MT9122 Sin Sout Rout Rin F0i C4i MT9122 in ST-BUS mode 1 Back-To-Back Configuration using D&C channel bypass MT9122 ...
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... ILC 3. 1.25 MT9122 Min Max Units -0 ±20 mA °C -65 150 500 mW ) unless otherwise stated. SS Test Conditions V V 400mV noise margin V 400mV noise margin V V °C Conditions/Notes µA ...
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... MT9122 AC Electrical Characteristics Voltages are with respect to ground (V ) unless otherwise stated. SS Characteristics 1 MCLK Clock High 2 MCLK Clock Low 3 MCLK Frequency Dual Channel Single Channel 4 BCLK/C4i Clock High 5 BCLK/C4i Clock Low 6 BCLK/C4i Period 7 SSI Enable Strobe to Data Delay (first bit) 8 SSI Data Output Delay (excluding first ...
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... CSSI t 100 CSSM t 100 CSH t 100 OHZ Symbol TTL Pin MCH t MCL Figure 16 Master Clock - MCLK MT9122 Units Test Notes =150pF =150pF L CMOS Pin Units - V 0.5 0.9 0.1 0.7 ...
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... MT9122 Bit 0 (1) Sout/Rout (2) BCLK SSS V (2) ENA1/ENA2 H or (2) V ENB1/ENB2 L Bit (3) Rin/Sin V L Notes: 1. CMOS output 2. TTL input compatible 3. CMOS input (see Table 8 for symbol definitions) (1) Sout/Rout V H (2) C4i F0iS F0iH V H (2) F0i ...
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... Figure 20 - MOTOROLA Serial Microport Timing Notes: 1. CMOS output 2. TTL input compatible 3. CMOS input (see Table 8 for symbol definitions) DATA OUTPUT DATA INPUT t t IDH SCH t SCL Figure 19 - INTEL Serial Microport Timing t SCH t SCL MT9122 ODD OHZ SCP CSH ...
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... MT9122 Notes: 28 Data Sheet ...
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