MT9123AE Zarlink Semiconductor, MT9123AE Datasheet
MT9123AE
Related parts for MT9123AE
MT9123AE Summary of contents
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... Echo Canceller B Figure 1 - Functional Block Diagram VSS PWRDN F0od MT9123 CMOS Dual Voice Echo Canceller Data Sheet ISSUE 1 October 1996 Ordering Information MT9123AP 28 Pin PLCC MT9123AE 28 Pin PDIP -40 ° °C conforming to ITU-T operates in two major modes: Linear/ Sout µ/A-Law ...
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MT9123 1 ENA1 28 2 ENB1 27 ENA2 ENB2 25 5 Rin 24 PDIP Sin 6 23 VSS MCLK 21 9 IC1 20 10 NLP 19 11 IC2 18 LAW FORMAT ...
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Data Sheet Pin Description (continued) Pin # Name 4 ENB2 SSI Enable Strobe / ST-BUS Mode for Sin/Rout (Input). This pin has dual functions depending on whether SSI or ST-BUS is selected. For SSI, this is an active high channel ...
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MT9123 Pin Description (continued) Pin # Name 19/20 S2/S1 Selection of Echo Canceller A Functional States (Input). Controllerless Mode: Selects Echo Canceller A functional states according to Table 2. Controller Mode: S2 and S1 pins become DATA2 and DATA1 pins ...
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Data Sheet Functional Description The MT9123 architecture contains two individually controlled echo cancellers (Echo Canceller A and B). They can be set in three distinct configurations: Normal, Back-to-Back and Extended Delay (see Figure 3). Under Normal configuration, the two echo ...
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MT9123 Adaptive Filter The adaptive filter is a 1024 tap FIR filter which is divided into two sections. Each section contains 512 taps providing 64ms of echo estimation. In Normal configuration, the first section is dedicated to channel A and ...
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Data Sheet NLPTHR = hex(NLPTHR (hex) (dec) where 0 < NLPTHR < 1 (dec) The comfort noise injection can be disabled by setting the INJDis bit Control Register 1. It should be noted that the NLPTHR is ...
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MT9123 Echo Canceller A Functional State S2/S1 (1) 00 Mute (2) 01 Bypass (1,3) 10 Disable Adaptation (3) 11 Enable Adaptation (1) Filter coefficients are frozen (adaptation disabled) (2) The adaptive filter coefficients are reset to zero (3) The MT9123 ...
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Data Sheet CONFIG1 CONFIG2 CONFIGURATION 0 0 (selects Controller Mode Extended Delay Mode 1 0 Back-to-Back Mode 1 1 Table 3 - Configuration in Controllerless Mode Controller Mode In Control Register 1, the Normal configuration can be programmed ...
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MT9123 Enable Strobe Pin Echo Canceller ENA1 A ENB1 B ENA2 A ENB2 B Table 5 - SSI Enable Strobe Pins PCM Law and Format Control (LAW, FORMAT) The PCM companding/coding law used by the MT9123 is controlled through the ...
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Data Sheet must be ignored. This also means that input data on the DATA2 pin is ignored by the MT9123 during a valid read by the Motorola processor. All data transfers through the microport are two bytes long. This requires ...
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MT9123 Function selected when pins CONFIG1 & 2 ≠ 00 Normal Configuration Set pins CONFIG1 to 1 and CONFIG2 1 to select this configuration. Back-to-Back Set pins CONFIG1 to 1 and CONFIG2 select Configuration this configuration. Extended ...
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Data Sheet C4i F0i F0od ECA PORT1 Rin Sout ECA PORT2 Sin Rout outputs=High impedance inputs = don’t care In ST-BUS Mode 1, both ...
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MT9123 C4i F0i 0 F0od PORT1 Rin Sout PORT2 Sin ...
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Data Sheet BCLK PORT1 ENA1 ENB1 Rin Sout PORT2 ENA2 ENB2 Sin Rout outputs=High impedance inputs = don’t care Note that the two ports are independent so that, for example, PORT1 can operate with 8 bit enable strobes and PORT2 ...
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MT9123 COMMAND/ADDRESS DATA 2 R Receive DATA 1 High Impedance Transmit SCLK CS Delays due to internal processor timing which are transparent to the MT9123. The MT9123: latches receive data on the ...
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Data Sheet Register Summary Echo Canceller A, Control Register 1 CRA1 Reset INJDis BBM Echo Canceller B, Control Register 1 CRB1 Reset INJDis BBM Extended- When high, Echo Cancellers A and B are internally ...
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MT9123 Echo Canceller A, Flat Delay Register Echo Canceller B, Flat Delay Register Echo Canceller A, Decay Step Number Register Echo Canceller B, Decay Step Number Register ...
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Data Sheet Echo Canceller A, Rin Peak Detect Register 2 Echo Canceller B, Rin Peak Detect Register Echo Canceller A, Rin Peak Detect Register 1 Echo Canceller B, Rin ...
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MT9123 Echo Canceller A, Double-Talk Detection Threshold Register 2 ADDRESS = 15h WRITE/READ VERIFY Echo Canceller B, Double-Talk Detection Threshold Register 2 ADDRESS = 35h WRITE/READ VERIFY DTDT DTDT DTDT DTDT Echo Canceller A, Double-Talk ...
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Data Sheet Applications MT8910 2B1Q MT8972 Bi-Phase MT8931 S-INT DSTo T R DSTi echo C4o F0b paths Figure 12 - (Basic Rate ISDN) Wireless Application Diagram MT9160 5V CODEC Dout T Din R F0i Clockin echo path MT9160 5V CODEC ...
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MT9123 MT9160 5V CODEC Dout T Din R F0i Clockin echo path MT9160 5V CODEC Dout T R Din Clockin F0i echo path MT8941 PLL F0 C4 Figure 14 - (Analog Trunk) Wireless Application Diagram MT8910 2B1Q MT8972 Bi-phase MT8931 ...
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Data Sheet Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any digital pin 3 Continuous Current on any digital pin 4 Storage Temperature 5 Package Power Dissipation * Exceeding these values may cause permanent damage. Functional operation under ...
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MT9123 AC Electrical Characteristics Voltages are with respect to ground (V ) unless otherwise stated. SS Characteristics 1 MCLK Clock High 2 MCLK Clock Low 3 MCLK Frequency Dual Channel Single Channel 4 BCLK/C4i Clock High 5 BCLK/C4i Clock Low ...
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Data Sheet AC Electrical Characteristics Characteristics 1 Input Data Setup 2 Input Data Hold 3 Output Data Delay 4 Serial Clock Period 5 SCLK Pulse Width High 6 SCLK Pulse Width Low 7 CS Setup-Intel 8 CS Setup-Motorola 9 CS ...
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MT9123 Bit 0 (1) Sout/Rout (2) BCLK SSS V (2) ENA1/ENA2 H or (2) ENB1/ENB2 V L Bit (3) Rin/Sin V L Notes: 1. CMOS output 2. TTL input compatible ...
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Data Sheet (1, 2) DATA1 t IDS V H (2) SCLK CSSI Notes: 1. CMOS output 2. TTL input compatible 3. CMOS input (see Table 8 for symbol definitions) V ...
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MT9123 Notes: 28 Data Sheet ...
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