MT9126 Zarlink Semiconductor, MT9126 Datasheet
MT9126
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MT9126 Summary of contents
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... PCM is provided to facilitate external DSP functions . Full Duplex ADPCM PCM Quad I/O Transcoder Control Decode MS1 MS2 MS3 A/ FORMAT Figure 1 - Functional Block Diagram MT9126 CMOS Quad ADPCM Transcoder Data Sheet ISSUE 3 April 2002 Ordering Information 28 Pin Plastic DIP 28 Pin SOIC - +85 C utilized conform to ...
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... MT9126 Pin Description Pin # Name 1 EN1 Enable Strobe 1 (Output). This 8 bit wide, active high strobe is active during the B1 PCM channel in ST-BUS mode. Becomes a single bit, high true pulse when LINEAR=1. In SSI mode this output is high impedance. 2 MCLK Master Clock (input). This is a 4.096 MHz (minimum) input clock utilized by the transcoder function ...
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... IC Internal Connection (Input). Tie to V Description transparent bypass of the ST-BUS D- and C- chan- SS the ST-BUS D-channel and C-channel output timeslots DD Law Select (Input). This input pin selects for normal operation. SS MT9126 Law companding when set 8-91 ...
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... MT9126 Pin Description Pin # Name 19 MS1 Mode Selects 1, 2 and 3 (Inputs). Mode selects for all four encoders. 20 MS2 MS3 MS2 21 MS3 Positive Power Supply. Nominally 5 volts +/-10 ADPCMi Serial ADPCM Stream ( Input). 128 kbit/s to 4096 kbit/s serial ADPCM word input stream ...
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... PCM port, and the ADPCMi/o port. The two PCM ports may transport 8-bit companded PCM or 16-bit linear PCM. The alignment of the channels is determined by the two input strobe signals ENB1 and ENB2/F0od. The bit clock (BCLK) and input strobes (ENB1 and ENB2/F0od) are common for all MT9126 to either ST-BUS or SSI ...
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... MT9126 three of the serial I/O ports. BCLK can be any frequency between 128 kHz synchronized to the input strobes. BCLK may be discontinuous outside of the strobe boundaries except when LINEAR=1. In LINEAR mode, BCLK must be 2048 kHz and continuous for 64 cycles after the ENB1 rising edge and for the duration of ENB2/ F0od ...
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... In 32 kbit/s and 24 kbit/s linear mode, the 16-bit Therefore uniform PCM dual-octets of the B1, B2, B3 and B4 channels (from PCMi1 and PCMi2) are compressed into four 4-bit words on ADPCMo. The four 4-bit ADPCM words of the B1, B2, B3 and B4 channels MT9126 th BCLK period). th bit period) while ENB2/F0od th ...
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... MT9126 from ADPCMi are expanded into four 16-bit uniform PCM dual-octets on PCMo1 and PCMo2. 16-bit uniform PCM are received and transmitted most significant bit first starting with b15 and ending with b0. ADPCM data are transferred most significant bit first starting with I1 and ending with I4 for 32 kbit/s and ending with I3 for 24 kbit/s operation (i.e don’ ...
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... B1 B2 SSS SEL = 1 MT9126 SEL for 16 kb/s only SSS ...
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... MT9126 BCLK ENB1 ENB2/F0od PCMi/o1 ADPCMo/i PCMi/o2 PCMi/o1 ADPCMo/i PCMi/o2 PCMi/o1 ADPCM o/i PCMi/ undetermined logic level output; don’t care input Outputs high impedance outside of channel strobe boundaries Two frame delay from data input to data output Figure 6 - SSI PCM and ADPCM Bypass Relative Timing ...
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... In 24 kb/s, bit 4 becomes “X” kb SEL operates for 16 kb/s only MT9126 ...
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... MT9126 MCLK (C4i) F0i C2o EN1 (output) F0od/ENB2 SSS PCMi/o1 B1 PCMi/o2 ADPCMi/o (32/24 kb/s) bit kbit/s ADPCMi/o (16 kb/s) outputs = High impedance inputs = don’t care X = undetermined logic level output; don’t care input Outputs high impedance outside of channel boundaries Two frame delay from data input to data output Note: D & ...
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... MT9126 ...
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... Total delay from data input to data output = 2 frames. 8-102 Applications Figure 11 depicts an ISDN line card utilizing the MT8910 ’U’ interface transciever and MT9126 ADPCM transcoder. This central office application implements the network end of a Pair-Gain system. Figure 12 shows Mitel devices used to construct the remote Pair-Gain loop terminator ...
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... F0i F0od F0od 2 1 Figure 11 - ISDN Line Card with 32 kbit/s ADPCM F0i LIN+ LIN- F0i F0b LOUT- MCLK C4b LOUT+ ADPCMi DSTo ADPCMo DSTi F0od F0od F0i F0od 8 MT9126 C4i F0i MT8980 F0i DX ST1i ST1o C4i ST2o ST2i 8-103 ...
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... MT9126 8-104 Data Sheet ...
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... MCLK (C4i) PCMo1 PCMo2 ADPCMo ADPCMi PCMi1 PCmi2 +5v LINEAR EN1 ENB2/F0od MT9126 C2o F0i MCLK (C4i) PCMo1 PCmo2 ADPCMo ADPCMi PCMi1 PCMi2 +5v LINEAR EN1 ENB2/F0od MT9126 C2o F0i MCLK (C4i) PCMo1 PCMo2 ADPCMo ADPCMi PCMi1 PCMi2 +5v LINEAR EN1 ENB2/F0od ADPCM BUS 8-105 ...
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... MT9126 Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any I/O pin 3 Continuous Current on any I/O pin 4 Storage Temperature 5 Package Power Dissipation * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics 1 Supply Voltage 2 TTL Input High Voltage ...
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... 122 F0iS t 50 122 F0iH x100 t DFD t 244 DFW t 61 C4P t DSD t 50 DSH t 50 DSS MT9126 Max Units Test Conditions ns ns 7900 =150pF//R = =150pF//R = BCL BCL ...
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... MT9126 t BCP BCLK S t SSS S ENB1 I or ENB2 PCMi/ADPCMi t SD PCMo/ADPCMo S MCLK F0iH U S F0i t F0iS F0od AC Electrical Characteristics Voltages are with respect to ground (V ) unless otherwise stated. SS Characteristics 1 Delay MCLK falling to C2o rising 2 Delay MCLK falling to Enable F0i MCLK (C4i) ...
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... Refer to Figure 14 for ST-BUS F0i timing. Figure 17 - ST-BUS Mode Select Set-up and Hold Timing † - Mode Select Timing (see Figures 16 & 17) † Sym Min Typ Max t 500 SU t 500 HOLD HOLD HOLD MT9126 Units Test Conditions ns MCLK=4096 kHz 8-109 ...
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... MT9126 Notes: 8-110 Data Sheet ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...