MT9160B Zarlink Semiconductor, MT9160B Datasheet
MT9160B
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MT9160B Summary of contents
Page 1
... A-Law and -Law requirements. Complete telephony interfaces are provided for connection to handset transducers. Internal register access is provided through a serial microport compatible micro-controllers. controllerless operation utilizing the default register conditions. The MT9160B/61B 2 ISO -CMOS consumption and high reliability. FILTER/CODEC GAIN ENCODER 7dB DECODER ...
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... D Data Input. A digital input for 8 bit wide channel data received from the Layer 1 in transceiver. Data is sampled on the falling edge of the bit clock during the timeslot defined by STB, or according to standard ST-BUS timing. Input level is CMOS compatible. 80 MT9160BE VBias VRef 2 23 ...
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... Inverting Microphone (Input). Inverting input to microphone amplifier from the handset microphone Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier from the handset microphone. 3, Connect . (24 Pin Packages only). Pin for MT9160B. 16,21 Overview The 5V Multi-featured Codec complete Analog/Digital and ...
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... MT9160B/61B In the event of PWRST, the MT9160B/61B defaults such that the side-tone path is off, all programmable gains are set to 0dB and ITU-T -Law is selected. Further, the digital port is set to SSI mode operation at 2048 kb/s and the FDI and driver sections are powered up. (See Microport section) ...
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... MT9160B/61B. The micro must discard non-valid data which it clocks in during a valid write transfer to the MT9160B/61B. During a valid read transfer from the MT9160B/61B data simultaneously clocked out by the micro is ignored by the MT9160B/61B. ...
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... The COMMAND/ADDRESS byte contains: Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire 84 Flexible Digital Interface A serial link is required to transport data between the MT9160B/61B and an external digital transmission device. The MT9160B/61B utilizes the ST-BUS architecture defined by Zarlink Semiconductor but DATA INPUT/OUTPUT ...
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... MT9160B/61B internal functions (i.e., Filter/Codec, Digital gain and tone generation) and to provide the channel timing requirements. The MT9160B/61B uses only the first four channels of the 32 channel frame. These channels are always defined, beginning with Channel 0 after the frame pulse, as shown in Figure 6 (ST-BUS channel assignments) ...
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... Layer 1 transferred MSB first on the ST-BUS by the which the MT9160B/61B. The full 64 kb/s bandwidth is available and is assigned according to which transceiver is being used. Consult the data sheet for the selected transceiver for its C-Channel bit definitions and order of bit transfer. When CEN is high, data written to the C-Channel register (address 05h) is transmitted, most signifi ...
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... V VI VII VIII III Di-bit Group Transmit D-Channel Power-up reset to 1111 1111 Figure 7c - D-Channel 8 kb/s Operation MT9160B/61B Microport Read/Write Access n+2 n+3 n+4* II III Power-up reset to 1111 1111 t =500 nsec max pullup Reset coincident with Read/Write of Address 04 Hex ...
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... Refer to the specifications of Figures 13& 14 for both synchronous and asynchronous SSI timing. PWRST/Software Reset (Rst) While the MT9160B/61B is held in PWRST no device control or functionality is possible. While in software reset (Rst=1, address 03h) only the microport is functional. Software reset can only be removed by writing the Rst bit low or by performing a hardware PWRST ...
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... MT9160B/61B Register Summary Address Bit 7 Bit 6 00 RxINC RxFG RxFG PDFDI PDDR 04 CEN DEN 07y - - Table Multi-featured Codec Register Map Gain Control Register 1 RxINC RxFG RxFG Receive Gain RxFG 2 Setting (dB) ...
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... STG STG STG STG STG STG ADDRESS = 02h WRITE/READ VERIFY - - - - DrGain MT9160B/61B Power Reset Value XXXX X000 0 Power Reset Value XX00 0000 90 ...
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... DEN. This control bit has significance only for ST-BUS mode and is ignored for SSI operation. D8 When high, D-channel operates at 8kb/s. When low, D-channel operates at 16kb/s (default). A/ When high, A-Law encoding/decoding is selected for the MT9160B/61B. When low, -Law encoding/decoding is selected. Smag/ITU-T When high, sign-magnitude code assignment is selected for the Codec input/output. When low, ITU-T code assignment is selected for the Codec input/output ...
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... Din HSPKR +/- Dout M +/- PCM/ANALOG = 1 Figure 8 - Loopback Signal Flows MT9160B/61B ADDRESS = 05h WRITE/READ Power Reset Value 1111 1111- write XXXX XXXX - read ADDRESS = 06h WRITE/READ Power Reset Value 1111 1111- write XXXX XXXX - read Power Reset Value XXXX 0000 HSPKR +/- ...
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... Twisted Pair Electret T Microphone Typical External Gain AV= 5- MT9160B + + Converter Lin MT8972 DNIC Z T Lout 10.24 MHz Figure 9 - Digital Telephone Set Advance Information 330 VBias + +5V ...
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... From Subscriber Line Interface MT9161B Converter Lin MT8972 DNIC Z T Lout MT9160B/61B Output to Subscriber Line Interface F0od DSTo F0i C4b Output to Subscriber Line Interface DSTi DSTo F0i C4b 94 ...
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... MT9160B/61B Absolute Maximum Ratings Parameter 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin (transducers excluded) 4 Storage Temperature 5 Power Dissipation (package) † Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions Characteristics 1 Supply Voltage ...
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... ‡ Min Typ Max 4095.6 4096 4096.4 MT9160B/61B ) unless otherwise stated. Max Units Test Conditions V 1 Max. Load = 10k V No load 1 0.9 See Note ...
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... MT9160B/61B † AC Characteristics for A/D (Transmit) Path - 3.14dB =1.843V for A-Law, at the Codec (V rms Characteristics 1 Analog input equivalent to overload decision 2 Absolute half-channel gain M to Dout Tolerance at all other transmit filter settings (1 to 7dB) 3 Gain tracking vs. input level ITU-T G.714 Method 2 4 Signal to total Distortion vs. input level ...
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... RR 0.25 -0.25 0.25 -0.90 0.25 -12.5 -25 D 240 AR D 750 DR 380 130 750 CT - -80 TR MT9160B/61B for -Law and 0dBm0 = A rms Lo3.14 Units Test Conditions Vp-p -Law Vp-p A-Law dB DrGain=0, RxINC =1* dB DrGain=0, RxINC =0* dB DrGain=1, RxINC =1* dB DrGain=1, RxINC =0* @ 1020 -40 dBm0 dB -40 to -50 dBm0 ...
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... MT9160B/61B AC Electrical Characteristics Characteristics 1 Absolute path gain gain adjust = 0dB 2 Tolerance of other side-tone settings (-9.96 to 9.96 dB) relative to output at 0dB setting † AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages. ‡ Typical figures are and are for design aid only: not guaranteed and not subject to production testing. ...
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... DSToD t 20 DSTiS t 50 DSTiH 1 bit cell C4P C4H C4L t t DSTiH DSTiS t F0iH Clock Periods Figure 11 - ST-BUS Timing Diagram MT9160B/61B Units Test Conditions 50pF, 1k load F0odS F0odH NOTE: Levels refer to %V ...
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... MT9160B/61B AC Electrical Characteristics Characteristics 1 BCL Clock Period 2 BCL Pulse Width High 3 BCL Pulse Width Low 4 BCL Rise/Fall Time 5 Strobe Pulse Width 6 Delayed Strobe Pulse Width 7 Strobe setup time before BCL falling 8 Strobe hold time after BCL falling 9 Delayed Strobe Pulse delay after ...
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... T DATA j DATA DATA1 DATA DATA +500ns-T j +(n- DATA DATA +500ns+T j +(n- DATA MT9160B/61B t DOLZ t t SSH DOHZ t DSTBF t DSTBR t ENWD (CMOS I/O) DD Max Units Test Conditions ns BCL=128 kHz ns BCL=256 kHz 600 ns T +600 ns C =150 pF, R =1K j ...
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... MT9160B/61B 70% STB 30% t dda2 t dha1 t dda1 70% Dout Bit 1 30% T DATA1 70% Din D1 30 DATA Figure 13 - SSI Asynchronous Timing Diagram AC Electrical Characteristics Characteristics 1 Input data setup 2 Input data hold 3 Output data delay 4 Serial clock period 5 SCLK pulse width high 6 SCLK pulse width low ...
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... Intel® and MCS-51® are registered trademarks of Intel Corporation Motorola® and SPI® are registered trademarks of Motorola Corporation National® and Microwire® are trademarks of National Semiconductor Corporation DATA INPUT DATA OUTPUT t CYC CYC DATA OUTPUT DATA INPUT Figure 14 - Microport Timing MT9160B/61B 90% 2.0V HiZ 0.8V 10% Intel t Mode = 0 ODD 2.0V 0.8V t OHZ 2 ...
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Package Outlines Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 8-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.115 (2.92) ...
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Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 22-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.125 (3.18) 0.195 ...
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16-Pin DIM Min Max Min A 0.093 0.104 0.093 (2.35) (2.65) (2.35) A 0.004 0.012 0.004 1 (0.10) (0.30) (0.10) B 0.013 0.020 0.013 (0.33) (0.51) (0.33) C 0.009 0.013 0.009 (0.231) (0.318) (0.231) D 0.398 0.413 ...
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... Fax: +65 333 6192 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...