MT9161 Zarlink Semiconductor, MT9161 Datasheet
MT9161
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MT9161 Summary of contents
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... Features • Improved idle channel noise over MT9160 • MT9161 version features a delayed framing pulse in SSI and ST-BUS modes to facilitate cascaded devices • Programmable -Law/A-Law Codec and Filters • Programmable ITU-T G.711/sign-magnitude coding • Programmable transmit, receive and side-tone gains • ...
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... DATA1 14 11 Din DATA2 13 12 Dout 24 PIN PDIP Figure 2 - Pin Connections Description /2) volts is available at this pin for biasing external DD SSA, SSA, SSD . Logically OR’ed with A/ register bit. DD Advance Information MT9161BE/BS/BN VBias VRef VSSA PWRST ...
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... STBd/ Delayed Frame Pulse Output . In SSI mode bit wide strobe is output after the FOod first strobe goes low. In ST-BUS mode, a frame pulse is output 4 channel time slots (MT9161B only) after /F0i CLOCKin Clock (Input). The clock provided to this input pin is used for the internal device functions ...
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MT9160B/61B In the event of PWRST, the MT9160B/61B defaults such that the side-tone path is off, all programmable gains are set to 0dB and ITU-T -Law is selected. Further, the digital port is set to SSI mode operation at 2048 ...
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Advance Information Filter/Codec and Transducer Interface Serial Port Receive Decoder Filter Gain PCM 2.05dB steps) in Transmit Filter PCM Transmit Filter Encoder Gain Gain -2.05dB ...
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... The COMMAND/ADDRESS byte contains: Figure 5 - Serial Port Relative Timing for Motorola Mode 00/National Microwire 84 Flexible Digital Interface A serial link is required to transport data between the MT9160B/61B and an external digital transmission device. The MT9160B/61B utilizes the ST-BUS architecture defined by Zarlink Semiconductor but DATA INPUT/OUTPUT ...
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... These channels are always defined, beginning with Channel 0 after the frame pulse, as shown in Figure 6 (ST-BUS channel assignments). The MT9161B provides a delayed frame pulse (F0od), 4 channels after the input frame pulse. The first two (D & C) Channels are enabled for use by the DEN and CEN bits respectively, (Control Register 2, address 04h) ...
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MT9160B/61B DEN: When 1, ST-BUS D-channel data ( bits/frame depending on the state of the D8 bit) is shifted into/ out of the D-channel (READ/WRITE) register. When 0, the receive D-channel data (READ) is still shifted into the ...
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Advance Information IRQ FP n-3 n-2 DSTo/ DSTi Di-bit Group I II Receive D-Channel No preset value * note that frame n+4 is equivalent to frame n of the next cycle. FP C4i C2 DSTo/ D0 ...
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... MT9160B/61B SSI Mode The SSI BUS consists of input and output serial data streams named Din and Dout respectively, a Clock input signal (CLOCKin), a framing strobe input (STB) and the MT9161B provides a delayed framing strobe output (STBd). The frame synchronous with, and eight cycles of, the bit clock. ...
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MT9160B/61B Register Summary Address Bit 7 Bit 6 00 RxINC RxFG RxFG PDFDI PDDR 04 CEN DEN 07y - - Table 2 ...
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Advance Information Gain Control Register Side-tone Gain Setting (dB) (default) OFF -9.96 -6.64 -3.32 0 3.32 6.64 9.96 STG = Side-tone Gain bit n n Path Control - - - ...
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MT9160B/61B Control Register 1 PDFDI PDDR Rst PDFDI When high, the FDI PLA and the Filter/Codec are powered down. When low, the FDI is active (default). PDDR When high, the ear driver and Filter/Codec are powered down. ...
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Advance Information C-Channel Register Micro-port access to the ST-BUS C-Channel information read and write D-Channel Register D7-D0 Data written to this register will be transmitted every frame, in ...
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MT9160B/61B Applications Figure 9 shows an application in a digital phone set. Various configurations of pair gain drops are depicted in Figures 12a and 12b using the MT9125 and MT9126, respectively. 330 + 0.1 F 511 100K ...
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... Twisted Pair VBias 0 0.1 F +5V A/ /IRQ CS SCLK DATA1 DATA2 DATA2 Motorola Mode only From Digital Phone Twisted Pair C4 Clock Input Figure 10 - Delayed Frame Pulse of First MT9161B Signalling Second MT9161B ( ) Typical External Gain From Subscriber AV= 5-10 Line Interface ...
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MT9160B/61B Absolute Maximum Ratings Parameter 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin (transducers excluded) 4 Storage Temperature 5 Power Dissipation (package) † Exceeding these values may cause permanent damage. Functional operation under ...
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Advance Information DC Electrical Characteristics Characteristics 1 Input HIGH Voltage CMOS inputs 2 Input LOW Voltage CMOS inputs 3 VBias Voltage Output 4 V Output Voltage Ref 5 Input Leakage Current 6 Positive Going Threshold Voltage (PWRST only) Negative Going ...
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MT9160B/61B † AC Characteristics for A/D (Transmit) Path - 3.14dB =1.843V for A-Law, at the Codec (V rms Characteristics 1 Analog input equivalent to overload decision 2 Absolute half-channel gain M to Dout Tolerance at all other transmit filter settings ...
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Advance Information † AC Characteristics for D/A (Receive) Path 3.14dB =1.843V for A-Law, at the Codec. (V rms Characteristics 1 Analog output at the Codec full scale 2 Absolute half-channel gain. Din to HSPKR Tolerance at all other receive filter ...
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MT9160B/61B AC Electrical Characteristics Characteristics 1 Absolute path gain gain adjust = 0dB 2 Tolerance of other side-tone settings (-9.96 to 9.96 dB) relative to output at 0dB setting † AC Electrical Characteristics are over recommended temperature range & recommended ...
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Advance Information AC Electrical Characteristics Characteristics 1 C4i Clock Period 2 C4i Clock High period 3 C4i Clock Low period 4 C4i Clock Transition Time 5 F0i Frame Pulse Setup Time 6 F0i Frame Pulse Hold Time 7 Delayed Frame ...
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MT9160B/61B AC Electrical Characteristics Characteristics 1 BCL Clock Period 2 BCL Pulse Width High 3 BCL Pulse Width Low 4 BCL Rise/Fall Time 5 Strobe Pulse Width 6 Delayed Strobe Pulse Width 7 Strobe setup time before BCL falling 8 ...
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Advance Information t t BCLH t R CLOCKin 70% (BCL) 30% t DIS 70% Din 30% t DOZL 70% Dout 30% t DOZH 70% STB 30% 70% STBd 30% Figure 12 - SSI Synchronous Timing Diagram AC Electrical Characteristics Characteristics ...
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MT9160B/61B 70% STB 30% t dda2 t dha1 t dda1 70% Dout Bit 1 30% T DATA1 70% Din D1 30 DATA Figure 13 - SSI Asynchronous Timing Diagram AC Electrical Characteristics Characteristics 1 ...
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Advance Information 2.0V 0.8V t IDS t IDH t CH SCLK t CSSI CS t CSSM t CH SCLK IDH t IDS 2.0V 0.8V Intel® and MCS-51® are registered trademarks of Intel Corporation Motorola® and SPI® are ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...