MT9300B Zarlink Semiconductor, MT9300B Datasheet
MT9300B
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MT9300B Summary of contents
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... Echo Canceller pools • DCME, satellite and multiplexer systems Description The MT9300B Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation requirements. The MT9300B architecture contains 16 groups of two echo cancellers (ECA and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds echo cancellation ...
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... ICO V Sout V ICO SS DD1 V Rin V Rout DD1 DD2 SS DD1 SS DD1 DD2 DD1 SS DD1 SS MT9300BV DD1 SS ...
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... P14,R2,R14, R15,R16,T1, T3,T7,T10, T14,T16 109 107 105 103 101 MT9300BL Figure 3 - 160 Pin MQFP Name 160 Pin MQFP V Ground. SS 149 MT9300B ...
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... MT9300B Pin Description (continued) Pin # 208-Ball LBGA A5,A9,B4,B10,C4,C8,C10,D3,D5, D7,D9,D11,D14,E13, F3,F4,F14,H3,H4,J13,J14,L13,L14 79, 93, 103, ,M3,M4,N6,N8, N10,N14, N15,P4,P6,P8, P10,P15, R4,R6,R8,R10, R12,T5,T12 E15,F15,A12,A10,A6,A2, 57, 59, 114, B1,B3,C1,C2,D2,E2,J2,K2,R1 A14,C15,D1,D15,E1,F1, G1 G15,H1,H15,J1,J15,K1, K15,L1,L15,F2 75, 78 86, 88 ...
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... TAP controller. This pin is pulled high by an internal pull-up when not driven. 153 TDI Test Serial Data In (3.3V Input). JTAG serial test instructions and data are shifted in on this pin. This pin is pulled high by an internal pull-up when not driven. MT9300B Description . SS . DD1 5 ...
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... TRST Test Reset (3.3V Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up or held low, to ensure that the MT9300B is in the normal functional mode. This pin is pulled by an internal pull-down when not driven. ...
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... DTDT is set internally to 0.5625 5dB). In some applications the return loss can be higher or lower than 6dB. The MT9300B allows the user to change the detection threshold to suit each application’s need. This threshold can be set by writing the desired threshold value into the DTDT register ...
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... Non-Linear Processor (NLP) After echo cancellation, there is always a small amount of residual echo which may still be audible. The MT9300B uses an NLP to remove residual echo signals which have a level lower than the Adaptive Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin) ...
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... A Rout Rin PORT1 PORT2 b) Extended Delay Configuration (128ms) Sin echo path Adaptive Filter (64ms) Rout PORT2 E.C.A c) Back-to-Back Configuration (64ms) Figure 6 - Device Configuration MT9300B echo canceller coefficients. This channel A + Sout - Adaptive Filter (128 ms) channel A Rin PORT1 Optional -12dB pad E.C.A Sout ...
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... The offset null filters can be disabled by setting the HPFDis bit to “1” in Control Register 2. ITU-T G.168 Compliance The MT9300B has been certified G.168 compliant in all 64 ms cancellation modes (i.e. Normal and Back- to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester. ...
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... MHz. The input and output data rate of the ST- Bus and GCI bus is 2.048 Mb/s. The 8 KHz input frame pulse can be in either ST- BUS or GCI format. The MT9300B automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS ...
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... MT9300B the bit cell (See Figure 10). In GCI format, every second rising edge of the C4i clock marks the bit boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 11). Base Base Echo Canceller A ...
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... Power Up Sequence On power up, the RESET pin must be held low for 100 s. Forcing the RESET pin low will put the MT9300B in power down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated. The 16 Main Control Registers, the Interrupt FIFO Register and the Test Register are reset to zero ...
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... Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only. Test Access Port (TAP) The TAP provides access to many test functions of the MT9300B. It consists of three input pins and one output pin. The following pins are found on the TAP. • Test Clock Input (TCK) The TCK provides the clock for the test logic ...
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... Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI TDO. • Device Identification register The Device Identification register provides access to the following encoded information: device version number, part number and manufacturer's name. MT9300B 15 ...
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... When low, output data on both Sout and Rout is a function of the echo canceller algorithm. 2 AdpDis When high, echo canceller adaptation is disabled. The MT9300B cancels echo. When low, the echo canceller dynamically adapts to the echo path characteristics Bits marked as “1” or “0” are reserved bits and should be written as indicated. ...
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... When high, data on Sout is muted to quiet code. When low, Sout carries active code. 0 MuteR When high, data on Rout is muted to quiet code. When low, Rout carries active code. Read/Write Address: 01 Read/Write Address HPFDis MuteS MuteR Reset Value: Description MT9300B + Base Address H + Base Address ...
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... MT9300B Echo Canceller A, Status Register Echo Canceller B, Status Register res TD DTDet res res Bit Name 7 res Reserved bit Logic high indicates the presence of a 2100Hz tone. 5 DTDet Logic high indicates the presence of a double-talk condition. 4 res Reserved bit. ...
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... FIR filter. The valid range 7-0 FD 128 in extended-delay mode. The default value Step Size (SS)] where 7-0 =4, then the exponential decay start value is 512 - [NS 2-0 MT9300B Read/Write Address Base Address H Read/Write Address Base Address H Power Reset Value 00 H ...
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... MT9300B Echo Canceller A, Control Register A3 Echo Canceller B, Control Register res res res res RingClr Bit Name 7-4 res Reserved bits. Must always be set to zero for normal operation. 3 RingClr When high, the instability detector is activated. When low, the instability detector is disabled. ...
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... Read Address: 10 Read Address MT9300B + Base Address H + Base Address H Power Reset Value N/A + Base Address H + Base Address H Power Reset Value N/A + Base Address H + Base Address H Power Reset Value N/A + Base Address H + Base Address H Power Reset Value ...
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... MT9300B Echo Canceller A, Double-Talk Detection Threshold Register 2 Read/Write Address: 15 Echo Canceller B, Double-Talk Detection Threshold Register 2 Read/Write Address DTDT DTDT DTDT DTDT Echo Canceller A, Double-Talk Detection Threshold Register 1 Read/Write Address: 14h + Base Address Echo Canceller B, Double-Talk Detection Threshold Register 1 Read/Write Address: 34h + Base Address ...
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... Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. Read/Write Address: 400 Format LAW PWUP Reset Value: Description . . MT9300B ...
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... MT9300B unused unused unused MTDBI MTDAI Main Control Register 1 Main Control Register 2 Main Control Register 3 Main Control Register 4 Main Control Register 5 Main Control Register 6 Main Control Register 7 Main Control Register 8 Main Control Register 9 Main Control Register 10 Main Control Register 11 ...
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... Interrupt FIFO Register. When low, normal operation is selected. Read Address Reset Value: Description Read/Write Address: 411 res res Tirq Reset Value: Description MT9300B 410 (Read only ...
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... MT9300B Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any 3.3V I/O pins (other than supply pins) 3 Voltage on any 5V Tolerant I/O pins (other than sup- ply pins) 4 Continuous Current at digital outputs 5 Package power dissipation 6 Storage temperature * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. ...
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... Serial Streams for ST-BUS and GCI Backplanes ‡ Sym Min Typ Max t 10 SIS 10 t SIH t 60 SOD t 30 ODE , with timing corrected to cancel time taken to discharge C L MT9300B Units Conditions Units Notes Units Test Conditions ...
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... MT9300B F0i t FPS C4i Rout/Sout Bit 0, Channel 31 Rin/Sin Bit 0, Channel 31 Figure 10 - ST-BUS Timing at 2.048 Mb/s F0i t FPS C4i Sout/Rout Bit 7, Channel 31) Sin/Rin Bit 7, Channel 31) Figure 11 - GCI Interface Timing at 2.048 Mb/s Sout/Rout 28 t FPW FPH t SOD Bit 7, Channel 0 Bit 6, Channel SIS ...
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... ADH t DDR t 3 DHR t 0 DSW t 0 DHW t AKD t 0 AKH t 20 IRD , with timing corrected to cancel time taken to discharge C L MT9300B ). unless otherwise stated. SS Units Notes MHz MHz Max Units Test Conditions =150pF, R ...
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... MT9300B DS CS R/W A0-A10 D0-D7 READ D0-D7 WRITE DTA IRQ Figure 14 - Motorola Non-Multiplexed Bus Timing 30 t CSS t RWS t ADS VALID ADDRESS t DDR VALID READ DATA t DSW VALID WRITE DATA t AKD t IRD Advance Information CSH RWH ADH DHR DHW V TT ...
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... 1.215 REF 15.00 0.20 R0.25 Typ. 0.54 0.05 Seating Plane C (0.36) 0.50 (3X) REF. Ø *The ball diamter and stand-off different 1.30 0.20 0.30 ~ 0.5 208-Ball LBGA - V-suffix MT9300B 0.40 ~ 0.60 (256X 1.00 15.00 17 ...
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... MT9300B Index Pin 1 160 Pin Metric Quad Flat Pack (MQFP Suffix 160-Pin Dim Min 0.01 (0.25) A2 0.125 (3.17) b 0.009 (0.22) D 1.23 BSC (31.2 BSC) D 1.102 BSC 1 (28.00 BSC) E 1.23 BSC (31.2 BSC) E 1.102 BSC 1 (28.00 BSC) e 0.025 BSC (0.65 BSC) L 0.029 (0.73) L1 0.063 REF (1.60 REF) NOTE: Governing controlling dimensions in parenthesis ( ) are in millimeters. ...
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... Fax: +65 333 6192 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...