MT933 Zarlink Semiconductor, MT933 Datasheet
MT933
Related parts for MT933
MT933 Summary of contents
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... Intelligent power management (auto shutdown, auto wake) G Low Transmit Jitter Description The MT933 is a single chip 3.3V CMOS physical layer solution from MII to the magnetics designed for 10BASE-T and 100BASE-TX Ethernet, based on the IEEE 802.3 specifications. The MT933 is compatible with the Auto Negotiation section of IEEE 802 ...
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... This data is synchronised to the rising edge of TX_CLK. To indicate that there is valid data for transmission on the MII, the MAC sets the TX_EN signal active. This forces the MT933 device to take in the data on the TXD[3:0] bus. This is serialised and directly encoded as Manchester data, before being output on the TXOP/TXON differential output for transmission through 1:Ö ...
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... The synthesizer is To indicate that there is valid data for transmission on the MII, the MAC sets the TX_EN signal active. This forces the MT933 device to take in the data on the TXD[3:0] bus and replace the first octet of the MAC preamble with Start-of-Stream Delimiter (SSD) symbols to indicate the start of the Physical Layer Stream ...
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... CRS de-assertion is between 19 and 23BT. 100Mb/s Transmit Errors If the MT933 detects that the TX_ER signal has gone active whilst the TX_EN signal is active, then it will propagate the detected error onto the cable by transmitting the symbol “ ...
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... Reset Mode There are two types of reset in the MT933 - hardware and software. The hardware reset is activated by setting the RESET_N pin to logic 0, and holding it low for at least 100ns. This mode causes an over-all reset in the MT933 - both analog and digital circuitry are reset ...
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... ANEN pin low or by setting bit 12 of register 0 to zero. If auto- neg is disabled, the MT933 will lose the link, and link will be re-established only after the MT933 control state machine has determined the speed using bits 13 and 8 of register 0 to determine speed and duplex respectively ...
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... RECOVERY DECODE ALIGNER RX100 CLOCK & & DATA DESCRAMBLE RECOVERY TX100 PISO TX100 SCRAMBLER ENCODER POWER ON CONTROLS RESET Figure 6 MT933 block diagram TX10 TX10 PULSE DRIVER RX10 FILTER & SIGNAL DETECT RX100 & SIGNAL DETECT RX100 EQUALIZER & BLW TX100 & ...
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... MT933 Pin list Pin # Name Type MD interface 20 RXIN Input 19 RXIP Input 28 TXON Output 23 TXOP Output 35 TXREF10 Input 36 TXREF100 Input 14 RESETN IOput 41 XTAL1 Input 40 XTAL2 Input MII interface 46 MDC Input 45 MDIO IOput 53 RX_CLK Output 55, 56, 57, 58 RXD0, RXD1, Output RXD2, RXD3 51 RX_DV ...
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... General The following is the register set that is implemented in the MT933 device: The interface to these registers is via the MDC and MDIO signals. The address of the MT933 is specified by the PA<4:0> static inputs The MD command is issued by the controller and can be read or write: command preamble start data ...
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... Remote fault 1.3 ANEG able 1.2 Link status 1.1 Jabber detect 1.0 Extended regs reg 2/3- MT933 Identifier register Bit Bit name 2.15:0 OUI 3.15:0 OUI/device ID 10 Description 1 = PHY able to perform 100BaseT4 0 = PHY not able to perform 100BaseT4 1 = PHY able to perform 100BASE- PHY not able to perform 100BASE- PHY able to perform 100BASE-TX ...
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... Test registers Bit Bit name 15:0 reserved Description Next page able - the MT933 is not able to perform next page remote fault detected 1= a remote fault been detected T4, 100Fdx, 100Hdx, 10Fdx, 10Hdx Description partner is next page capable partner sent an acknowledge bit partner detected a remote fault partner’ ...
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... MT933 reg 21 - MII interrupt control register Bit Bit name 21.15:0 Clear Interrupt reg 22 Test registers Bit Bit name 15:0 reserved reg 24- MT933 specific register Bit Bit name 24.15:14 PWRCON[1:0] 24.13 MINTPOL 24.12 Pol Dis 24.11 SQE disable 24.10 JAB disable 24. 9 loop 10 24.8 Force RX 24.7 Force TX 24.6 CRS_CTL 24.5 MF 24.4 Byp ALIGN 24 ...
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... ANEG state machine current state Description number of RX_ERR events since last read - Clears either in change of speed or read of this reg. Description the disconnect mechanism status number of False CRS events since last read. Active only when DISCEN = 1”. Description test mode only MT933 Default R PA<4:0> ...
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... MT933 Operating Conditions Supply voltage Ambient temperature DC Electrical Characteristics Recommended operating conditions apply except where stated. Characteristic DC parameters - input High level input voltage Low level input voltage High level input current Low level input current Pin capacitance to ground DC parameters - output -6mA buffers ...
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... Typ Max 80 85 130 180 125 130 130 135 MT933 Units Conditions MHz % MHz 100Mbs mode % 100Mbs mode MHz 10Mbs mode % 10Mbs mode MHz 100Mbs mode % 100Mbs mode MHz 10Mbs mode % 10Mbs mode MHz ns mA Measured at 3.3V ...
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... External capacitors are required on the XTAL1 & XTAL2 pins. Manufacturer's recommendations should be followed. Tracking to the crystal and the capacitors must be as short as possible. Other signal paths must not cross the area. The MT933 is supported by the following magnetics: VENDOR Pulse MINT Vdd DVDD3 ...
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... Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...