MT933CG Zarlink Semiconductor, MT933CG Datasheet
MT933CG
Related parts for MT933CG
MT933CG Summary of contents
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This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ ...
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Features G Integrated 10/100 Mbps Ethernet in a Single Chip Solution G Single 3.3V Power Supply G Half Duplex and Full Duplex in both 10BASE-T and 100BASE-TX G Full MII for a Glueless MAC Connection G Extended Register Set G ...
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MT933 SUBGND2 1 TX_ER 2 DGND1 3 TX_EN 4 LNKST 5 ACTST 6 COLST 7 DVDD1 8 RXVDD3 9 RXGND3 10 FDST 11 SPDST 12 RESETN 14 RXVDD2 15 RXGND2 16 Functional Description The MT933 has three basic modes of ...
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The Manchester data stream will be decoded into a 4- bit parallel data bus, RXD[3:0]. The RXD bus is clocked out on RX_CLK rising. The MT933 must detect the first 4 bits of pre-amble before RX_DV is set high. When ...
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MT933 TX100 PISO, Encoder and Scrambler Data from the MII is loaded into the TX100 PISO, Encoder and Scrambler on the rising edge of TX_CLK converted to serial MLT3 for outputting to the TX100 Driver. The TXD[3] bit ...
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TX_EN TX_ER TXD [3: ignored 1 0 0000 through 1111 1 1 0000 through 1111 Transmit error propagation Figure 3. 100Mb/s Transmit Error States 100Mb/s Receive Errors When there is no data on the cable, the receiver will ...
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MT933 Low-Power Mode This function is set via the management interface. Using MDC and MDIO, Bit 11 of register 0 is written high to put the MT933 into Low-Power mode. The type of low power mode is dependant on bits ...
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TXD3-0 FRAMING TX_ER TX_EN CONTROL TX_CLK CLOCK GEN. FRAMING CONTROL CRS COL FRAMING RXD3-0 & 5B4B RX_ER DECODE RX_DV RX_CLK FRAMING &4B5B ENCODE TX100 CLOCK GEN. Internal ACTST clock LNKST COLST LEDS FDST SPDST OSC MANCHESTER & ENCODER SHAPER TX10 ...
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MT933 Pin list Pin # Name Type MD interface 20 RXIN Input 19 RXIP Input 28 TXON Output 23 TXOP Output 35 TXREF10 Input 36 TXREF100 Input 14 RESETN IOput 41 XTAL1 Input 40 XTAL2 Input MII interface 46 MDC ...
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General The following is the register set that is implemented in the MT933 device: The interface to these registers is via the MDC and MDIO signals. The address of the MT933 is specified by the PA<4:0> static inputs The MD ...
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MT933 reg 1- status register Bit Bit name 1.15 100BaseT4 1.14 100BASE-TX - FDX 1.13 100BASE-TX - HDX 1.12 10BASE-T - FDX 1.11 10BASE-T - HDX 1.10 100BaseT2 - FDX 1.9 100BaseT2 - HDX 1.8:7 Reserved 1.6 MF preamble suppression ...
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ANEG advertisement register Bit Bit name 4.15 NP 4.14 reserved 4.13 remote fault 4.12:10 reserved 4.9:5 Technology 4.4:0 selector field reg 5- ANEG link partner ability register Bit Bit name 5.15 NP 5.14 ACK 5.13 remote fault 5.12:5 ...
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MT933 reg 21 - MII interrupt control register Bit Bit name 21.15:0 Clear Interrupt reg 22 Test registers Bit Bit name 15:0 reserved reg 24- MT933 specific register Bit Bit name 24.15:14 PWRCON[1:0] 24.13 MINTPOL 24.12 Pol Dis ...
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ANEG status Bit Bit name 25.15:14 reserved 25.13 Pol 25.12:8 PA 25.7 aneg complete 25.6 Duplex 25.5 speed 25.4 ability mtc 25.3:0 ANEG state reg 26 - Symbol error counter Bit Bit name 26.15:0 RX_ERR counter reg ...
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MT933 Operating Conditions Supply voltage Ambient temperature DC Electrical Characteristics Recommended operating conditions apply except where stated. Characteristic DC parameters - input High level input voltage Low level input voltage High level input current Low level input current Pin capacitance ...
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AC Electrical Characteristics (continued) Recommended operating conditions apply except where stated. Characteristic REFCLK Frequency Duty cycle RXCLK Frequency Duty cycle Frequency Duty cycle TXCLK Frequency Duty cycle Frequency Duty cycle MDC Frequency Minimum high/low Supply Current 10Base-T Idle 10Base-T Active ...
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MT933 SUBGND2 TX_ER DGND1 TX_EN LNKST Vdd ACTST Vdd COLST Vdd DVDD1 RXVDD3 RXGND3 FDST Vdd SPDST PA4 10K(5%) RESETN Vdd 5K(5%) RXVDD2 RXGND2 EXTERNAL COMPONENTS Connecting an External 25MHz Reference If an external clock is used then it should ...
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... Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...