TSS463 ATMEL Corporation, TSS463 Datasheet
TSS463
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TSS463 Summary of contents
Page 1
... TSS463B. Messages are encoded in enhanced Manchester code, and an optional pulsed code for use with an optical or radio link maximum bit rate of 1 Mbit/s. The TSS463B analyzes the messages received or transmitted according to 6 different criteria includ- ing some higher level checks. ...
Page 2
... Block Diagram TSS463B 2 4102E–AUTO–12/04 ...
Page 3
... XTAL2 64 TEST/VSS 7 CKOUT 8 RXD1 9 RXD2 10 RXD0 11 TXD 12 GND 13 RESET 14 SCLK 15 MOSI 16 TSS463B TOP VIEW 16 MOSI 15 SCLK 14 RESET 13 GND 12 TXD 11 RXD0 10 RXD2 RXD1 9 Pin Function SPI/SCI Data Output SPI/SCI Slave Select (active low) Interrupt (active low power supply Crystal oscillator or clock input pin ...
Page 4
... CKOUT 8 Notes: 1. The TSS463B RESET pin can be either connected to GND through a 1 µF capacitor, or the µC RESET pin or unconnected (inactive with internal pull-up). 2. Leaving MISO output pin floating in high impedance mode slightly increases standby consumption. A 100K pullup/pulldown resistor is recommended. ® ...
Page 5
... Interface Modes Motorola SPI Mode 4102E–AUTO–12/04 The processor controls the TSS463B by reading and writing the internal registers of the circuit. These registers appear to the processor as regular memory locations. The TSS463B must be connected with an SPI or SCI serial interface.The following sec- tion provides information switching from one mode to another. ...
Page 6
... The SS pin is the slave chip select low active. A low state on the Slave Select input allows the TSS463B to accept data on the MOSI pin and send data on the MISO pin. The Slave Select signal must not toggle between each transmitted byte and should be left at a low level during the whole SPI frame ...
Page 7
... Address, Address + 1, Address + 2, ..., Address + n with 28). To make sure the TSS463B is not out of synchronization, the SPI interface will transmit data ’0xAA’and ’0x55’on the MISO pin during address and control byte time. This way, the master always ensures the TSS463B is well-synchronized ...
Page 8
... When the master (CPU) conducts a read, it sends an address byte, a control byte and dummy characters (’0xFF’for instance) on its MOSI line. In the case of a VAN messages RAM read (VAN frame received), the first data byte sent back by the TSS463B on its MISO pin is the data length so the master knows how many dummy characters it must send to read the VAN frame properly ...
Page 9
... It is the only exception of this mode compared with the Motorola SPI mode. The SCI mode is the third type of interface. The TSS463B enters this mode if the Initial- ization Sequence contains (first two bytes received) ’0x00, 0xFF’. ...
Page 10
... not asserted, MISO pin is in high impedance state and incoming data is not driven to the serial data register. Same as the SPI protocol described before except for data arranging (LSB first and MSB last). Only 8 bits are monitored by the TSS463B and master must monitor the 8 first bits th too (9 bit always equal to 1). ...
Page 11
... Control 8 Xtal Min ( MHz event occurs in the TSS463B that needs the attention of the processor, this will be signalled on the active low, open drain interrupt request pin. The event that creates this request is controlled by the internal registers. Every time the microprocessor accesses any of the interrupt registers (addresses 0x08 to 0x0B), the INT pin will be released momentarily ...
Page 12
... XTAL Min 0xFF An oscillator is integrated in the TSS463B, and consists of an inverting amplifier of that the input is XTAL1 and the output XTAL2. A parallel resonance quartz crystal or ceramic resonator must be connected to these pins. As shown in Figure 5, two capacitors have to be connected from the crystal pins to ground ...
Page 13
... TSS463B 4 MHz 2 MHz KTS/s Kbits/s KTS/s 250 200 125 125 100 62.50 62.50 50 31.25 31.25 25 15.625 15.625 12.5 7.813 7.813 6.25 3.906 3.906 3.125 1.953 1 ...
Page 14
... The data on the line is encoded according to the VAN standard ISO/11519-3. This means that the TSS463B is using a two level signal having a recessive (1) and a domi- nant (0) state. Furthermore, due to the simple medium used, all data transmitted on the bus is also received simultaneously. ...
Page 15
... Slave DATA Figure 12 shows a normal VAN bus frame initiated with a Start Of Frame (SOF) sequence shown in Figure 14. The SOF can only be transmitted by an autonomous module. During the preamble, the TSS463B will synchronize its bit rate clock to the data received. Frame Data ...
Page 16
... PRESCALED CLOCKS 0 The IFS is defined minimum of 64 prescaled clock periods. The TSS463B, accepts an IFS of zero prescaled clocks for the reception only of a SOF sequence. Once the bus has been determined as being free, the module must autono- mous module, emit an SOF sequence or synchronous access module, wait until it detects a preamble sequence ...
Page 17
... In order to conform with the standard a received frame included the combination R/W. RTR = 01 is ignored without any IT generation. All the bits in the command field are automatically handled by the TSS463B, so the user does not need to be concerned for encoding and decoding these bits. The command bits transmitted on the VAN bus are calculated from the current status of the active message ...
Page 18
... However, since the CRC is calculated automatically from the identifier, command and data fields by the TSS463B, it need not concern the user of the circuit. When the frame check sequence has been transmitted, the transmitting module must transmit an End Of Data (EOD) sequence, followed by the ACKnowledge field (ACK) and the End of Frame sequence (EOF) to terminate the transfer ...
Page 19
... Dominant for no acknowledge from Transmitter R/W : Dominant from Transmitter RTR : Dominant from Transmitter - (*) Manchester bit ACK : Absent from Transmitter and from Receiver because RAK is Dominant 4102E–AUTO–12/04 IDENTIFIER DATA IDENTIFIER DATA IDENTIFIER DATA IDENTIFIER DATA TSS463B CRC EOF CRC EOF CRC EOF CRC EOF 19 ...
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... Bus EXT : Recessive from Requestor RAK : Recessive for acknowledge from Requestor R/W : Recessive from Requestor RTR : Recessive from Requestor - (*) Manchester bit ACK : Absent from Requestor and Positive from Requestee because RAK is Recessive TSS463B 20 IDENTIFIER DATA IDENTIFIER DATA IDENTIFIER IDENTIFIER CRC CRC CRC ...
Page 21
... Recessive from Replyer RAK : Recessive for acknowledge from Replyer R/W : Recessive from Replyer RTR : Dominant from Replyer ACK : Absent from Replyer and Positive from Receiver because RAK is Recessive 4102E–AUTO–12/04 IDENTIFIER DATA IDENTIFIER DATA - (*) Manchester bit TSS463B CRC EOF CRC EOF 21 ...
Page 22
... In specified selection mode, every RI pulse when an EOF is detected or through an active SDC automatic selection mode and SDC active, no failure sampled by 2 consecutive SDC rising edges. - General reset. TSS463B 22 The purpose of the diagnosis system is to detect any short or open circuits on either the DATA or DATA lines and to permit possible, to carry the communications on the non-defective line ...
Page 23
... Synchronous diagnosis The synchronous diagnosis counts the number of edges on the data input connected to the reception logic during one SDC period. If there are less than four edges during one SDC period, the diagnosis mode will change to the major error mode. TSS463B th of timeslot). 23 ...
Page 24
... Signals RI Signal (Return to Idle) SDC Signal (Synchronous Diagnosis Clock) TIP Signal (Transmission in Progress) TSS463B 24 • Transmission diagnosis The transmission compares RxD1 and RxD2 inputs (through the input comparators and the filters) with the data transmitted on TxD output time when the transmission logic generates a dominant - recessive transition, the inputs can give different values ...
Page 25
... Four programming modes determine how to use the three different inputs and the diag- nosis system. • 3 specified selection modes • 1 automatic selection mode Table 4. Programming Modes Ma Mb Operating Mode 0 0 Differential communication 0 1 Degraded communication on RxD2 (DATA Degraded communication on RxD1 (DATA Automatic selection according the diagnosis status TSS463B 25 ...
Page 26
... Value after RESET is found after register name value is given, the register is not initialized at RESET. TSS463B 26 The TSS463B memory map consists of three different areas, the Control and Status registers, the Channel registers and the Message data (or Mailbox). Channel 13 Channel 13 ...
Page 27
... The user can invert the logical levels used on either the TxD output or the RxD inputs in order to adapt to different line drivers and receivers. One: A one on either of these bits will invert the respective signals. Zero: (default at reset) The TSS463B will set TxD to recessive state in Idle mode and consider the bus free (recessive states on RxD inputs). 7 ...
Page 28
... The three different module types are supported (see “VAN Frame” on page 15): One: The TSS463B is at once an autonomous module (Rank 0), a synchronous access module (Rank slave module (Rank 16). Zero: The TSS463B is at once an synchronous access module (Rank slave mod- ule (Rank 16). 7 ...
Page 29
... Example: For VAN frame speed rate = 62,5 KTS µs), SDC >100 ms => 100 µs = 6250, divider chosen: 8192, SDC [3:0] = 0111. Table 7. Diagnosis System Command Bits TSS463B Divide by 64 128 256 512 1024 2048 4096 8192 16384 32768 65536 ...
Page 30
... Activate Commands”, page 51). If the user sets the Idle bit, the circuit will enter idle mode. In idle mode the oscillator will operate, but the TSS463B will not transmit or receive anything on the bus, and the TxD output will be in tri-state ...
Page 31
... Sc is set. The only ways to reset this status bit is through the RI signal or a general reset. If this status bit is active, it indicates that the TSS463B has chosen an identifier to trans- mit, and it will continue to make transmission attempt for this message until it succeeds or the retry count is exceeded ...
Page 32
... Transmission Status Register (0x05) NRT [3:0] IDT [3:0] Last Message Status Register (0x06) NRTR [3:0] IDTR [3:0] Last Error Status Register (0x07) BOC: Buffer occupied TSS463B NRT3 NRT2 NRT1 • Read only register. • Default value after reset: 0x00. • The transmission Status register contains the number of retries made up-to-date, according to the Table 5 ...
Page 33
... FCSE indicates a mismatch between the FCS received and the FCS calculated One: FCSE active Zero: FCSE inactive ACKE indicates a physical violation or collision on ACK field of the frame when the TSS463B is a producer. One: ACKE active Zero: ACKE inactive Figure 23. ACKE Status Bit ...
Page 34
... Interrupt Status Register (0x09) RST: Reset Interrupt TE: Transmit Error Status Flag (or Exceeded Retry) TOK: Transmit OK status flag TSS463B 34 Figure 24. FV Status bit EOD field Expected Received Received Received EOD field Expected Received Received Received RST X X • Read only register. ...
Page 35
... One: Status flag reset. Zero: Status flag unchanged. One: Status flag reset. Zero: Status flag unchanged. One: Status flag reset. Zero: Status flag unchanged TEE TOKE REE ROKE TER TOKR RER ROKR TSS463B 1 0 RNOKE 1 0 RNOKR 35 ...
Page 36
... Figure 26. Update of the Status Register RST TE Internal RESET Flag Write TEE RSTR 4 TS BUS INT TSS463B 36 One: Status flag reset. Zero: Status flag unchanged. One: Status flag reset. Zero: Status flag unchanged. One: Status flag reset. Zero: Status flag unchanged. TOK RE Flag Flag ...
Page 37
... The base_address of each set is [0x08 * channel_number]). When the TSS463B is reset either via the external RESET pin or the general reset com- mand, the channel registers are not affected. That is, on power-up of the circuit, all the channel registers start with random values. ...
Page 38
... Message Pointer Register DRAK: Disable RAK (Used in ‘Spy Mode’) M_P [6:0]: Message Pointer TSS463B 38 The identifier tag and command registers are located at the base_address and base_address + 1. It allows the user to specify the full 12-bit identifier field of the ISO standard and the 4-bit command. ...
Page 39
... RTR bits of the command register (base_address + 0x01), they define the message type of this channel (see section “Message Types” on page 44 general rule, the status bits are only set by the TSS463B, so the user must reset them to perform a trans- mission (CHTx) or/and a reception (CHRx). The received and transmitted bits are only set if the corresponding frame is without errors or if the retry count has been exceeded ...
Page 40
... Identifier Mask Registers ID_M [11:0]: Identifier Mask TSS463B 40 The Identifier Mask registers (base_address + 0x06 and base_address + 0x07) allow bitwise masking of the comparison between the identifier received and the identifier specified ID_M 3 ID_M 2 ID_M 1 ID_M ID_M 11 ID_M 10 ID_M 9 ID_M 8 • ...
Page 41
... Length And Status Register”). This area is a pure RAM, it contains a random value after reset. Message Received DATA n Received DATA 0 RAK RNW RTR M_L [4..0] = n+1 received received received received DATA 0 Message Pointer Register M_P [6..0] DRAK M_P + 0x80 + M_P + 0x80 FCS DATA n TSS463B EOF 41 ...
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... CHER CHTx CHRx M_L [4..0] SOF ID [11..0] Transmitted DATA Frame Message Status (Pointed by: Message Pointer Register) RRAK: Received RAK Bit RRNW: Received RNW Bit RRTR: Received RTR Bit RM_L[4:0]: Message Length of the Received Frame TSS463B 42 Message DATA n Transmitted Transmitted (Nothing) DATA RRAK ...
Page 43
... Note the length reserved (in the message length and status register) for an incoming frame is 2 bytes greater or more, the TSS463B will write the 2 bytes of the CRC field in the message string just after DATAn. Because the VAN frame does not contain a message length, the only way for the component to know the length of the DATA field is either the message length register value, or the EOD field detection ...
Page 44
... In the first case no other modules on the bus responded with an in-frame reply, and in this case the TSS463B will set the message type to the after transmission state. When this message type is programmed, the TSS463B will listen on the bus for a deferred reply frame matching this identifier, without transmitting the reply request. ...
Page 45
... After reception 1 In the third case the TSS463B has not yet started to transmit the reply request, when another module either requests a reply, and gets it, or transmits a deferred reply. Warn- ing! This should be avoided as it may result in an illegal message type (Illegal reply Request) ...
Page 46
... The priority handling on the VAN bus itself is already explained in the Line interface sec- tion. The priorities for the messages in the TSS463B is however slightly different. For instance, it’s possible that an identifier matches two or more of the identifiers pro- grammed into the registers. In this case the lowest identifier number that has priority ...
Page 47
... If Ch8 the retry loop and the user wants to transmit the Ch5 without waiting the end of the loop, the user can use the rearbitrate command. • The TSS463B will then wait until the end of the current transmission, reload the retries counter and enable the Ch5 to transmit. • ...
Page 48
... IT generation) If the user sets the idle bit anywhere (after rearbitrate), the idle mode is entered only at the end of all the transmit attempts (for more information about idle command, see “Activate, Idle and Sleep Modes” on page 51). TSS463B 48 Delay ...
Page 49
... Figure 33. Disable Channel After Rearbitrate Delay Viol In this case, the TSS463B completes the current attempt (Ch8) and lets the transmission go into the new channel (Ch5 if validated), otherwise it stops all attempts on the current channel. Abort 4102E–AUTO–12/04 Ex: ACK Error (not seen by application) ...
Page 50
... Figure 34. Abort Example TSS463B 50 12 Timeslots 4102E–AUTO–12/04 ...
Page 51
... To exit from this mode the user must apply either an hardware reset (external reset pin) either an asynchronous software reset (via the SPI/SCI interface typical application (see Figure 5), using the CKOUT feature (pin 8), if the TSS463B is put in sleep mode, the clock provided to the microcontroller is stopped. So, the system does not run and the only way to awake this application is an external reset ...
Page 52
... ID_Tag i (msb) This Message area sharing permits either to optimize the allocation of the 128 bytes of DATA, either to perform some spe- cial communications between the different nodes of the network. TSS463B 52 The linkage feature allows two channels to share the same Message area, the message pointer and the message length assumes this property: • ...
Page 53
... Max Unit 0.3·V V CC·min versus Clock frequency. CC TSS463B Test Conditions see Table I = 3.2 mA, V min -3.2 mA, V min < V < < V < Note 4 Not tested (Note 1) (Notes ...
Page 54
... TSS463B 54 Figure 37 Figure 38. I versus Clock Frequency at 125 KTimeslot/s CCOP mA 9 8.5 8 7.5 MHz 4102E–AUTO–12/04 ...
Page 55
... Data Hold Time (Outputs After Enable Edge INT Float Pulse Width IZIL Note: 1. Simulated Data t CYC t LEAD t W(SCKL) t W(SCKH MISO IZIL float pulse only when address is 0x08 to 0x0B TSS463B = 0V SS Min Max 125 250 - 100 - 100 - ...
Page 56
... Interface Oscillator Characteristics External Clock Drive Characteristics (XTAL1) TSS463B 56 Figure 39. C2 versus Frequency pF 200 100 (no capacitance needed) see Note: Symbol Parameter t Oscillator period CHCH t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL V IH XTAL1 MHz ...
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... Packaging Information SO16 4102E–AUTO–12/ 2.35 A1 0.10 B 0.35 C 0.23 D 10.10 E 7.40 e 1.27 H 10.00 h 0. TSS463B Inch 2.65 0.093 0.30 0.004 0.49 0.014 0.32 0.009 10.50 0.398 7.60 0.291 BSC 0.050 10.65 0.394 0.75 0.010 1.27 0.016 0.104 0.012 0.019 0.013 0.413 0.299 BSC 0.419 0.029 0.050 57 ...
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... Ordering Information Part Number Supply Voltage TSS463B-TESA-9 TSS463B-TERA-9 (1) TSS463B-TERZ-9 Note: 1. These products are available in ROHS version. TSS463B 58 Temperature Range 5V +10% -40°C - +125°C 5V +10% -40°C - +125°C 5V +10% -40°C - +125°C Package Packing SO16 Stick SO16 Tape and Reel SO16 Tape and Reel ...
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... Atmel Corporation 2003. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...