MD2241-D128-V3 M-Systems Inc., MD2241-D128-V3 Datasheet - Page 13

• Manufacturer Part Number: MD2241-D128-V3
• Description: Diskonchip Dimm Plus
• Manufacturer: M-Systems Inc.

3.2
The system interface block provides an easy-to-integrate SRAM-like (also EEPROM-like) interface to DiskOnChip,
enabling it to interface with various CPU interfaces, such as a local bus, ISA bus, SRAM interface, EEPROM
interface or any other compatible interface. In addition, the EEPROM-like interface enables direct access to the
Programmable Boot Block to permit XIP functionality during system initialization.
A 13-bit wide address bus enables access to the DiskOnChip 8KB memory window (as shown in section 6.2). The
16-bit data bus permits full 16-bit wide access to the flash, due to an internal, dual-bank, interleaved-operation
architecture. With both internal and external 16-bit access, DiskOnChip DIMM Plus provides unrivaled
performance.
The Chip Enable (CE#), Write Enable (WE#) and Output Enable (OE#) signals trigger read and write cycles. A
write cycle occurs while both the CE# and the WE# inputs are asserted. Similarly, a read cycle occurs while both the
CE# and OE# inputs are asserted. Note that DiskOnChip DIMM Plus does not require a clock signal. DiskOnChip
features a unique analog static design, optimized for minimal power consumption. The CE#, WE# and OE# signals
trigger the controller (e.g., system interface block, bus control and data pipeline) and flash access.
The Reset In (RSTIN#) and Busy (BUSY#) control signals are used in the reset phase. See section 5.2 for details.
DiskOnChip DIMM Plus contains several configuration signals. The Interface Configuration (IF_CFG) signal
configures DiskOnChip for 16-bit or 8-bit mode of operation (see section 9.3.4). The Lock (LOCK#) signal enables
hard-wire hardware-controlled protection of code and data, as described below on protection and security-enabling
features.
3.3
The Configuration Interface block enables the designer to configure the DiskOnChip to operate in certain modes.
The IF_CFG pin is used to configure the device for 8/16 bit access mode and the LOCK# pin is used for hardware
write/read protection.
3.4
The Protection and Security-Enabling block, consisting of read/write protection, Unique ID and OTP area, enables
advanced data and code security and protection. Located on the main route of traffic between the host and the flash,
this block monitors and controls all data and code transactions to and from DiskOnChip.
3.4.1 Read/Write Protection
Data and code protection is implemented through a Protection State Machine (PSM). The user can configure one or
two independently programmable areas of the flash memory as read protected, write protected, or read/write
protected.
A Protection Area may be protected by either/both of these hardware mechanisms:
The size and location of each area is user-defined to provide maximum flexibility for the target platform and
application requirements.
The configuration parameters of the protected areas are stored on the flash media and are automatically downloaded
from the flash to the PSM upon power-up, to enable robust protection throughout the flash lifetime.
In the event of an attempt to bypass the protection mechanism, illegally modify the protection key or in any way
sabotage the configuration parameters, the entire DiskOnChip becomes both read and write protected, and is
completely inaccessible.
For further information on the hardware protection mechanism, refer to section 4.
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System Interface
Configuration Interface
Protection and Security-Enabling Features
64-bit Protection Key
Hard-wired LOCK# signal
Preliminary Data Sheet, Rev. 1.2
DiskOnChip DIMM Plus
94-SR-002-08-8L