DS3930 Maxim Integrated Products, DS3930 Datasheet - Page 10

• Manufacturer Part Number: DS3930
• Description: DS3930 Hex Nonvolatile Potentiometer With I/o And Memory
• Manufacturer: Maxim Integrated Products

terminated with a stop condition. The number of data
bytes transferred between start and stop conditions is
not limited and is determined by the master device. The
information is transferred byte-wise and each receiver
acknowledges with a ninth bit.
Within the bus specifications, a regular mode (100kHz
clock rate) and a fast mode (400kHz clock rate) are
defined. The DS3930 works in both modes.
Acknowledge: Each receiving device, when addressed,
is obliged to generate an acknowledge after the byte has
been received. The master device must generate an
extra clock pulse that is associated with this acknowl-
edge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is a stable low during the high period
of the acknowledge-related clock pulse. Of course,
setup and hold times must be taken into account. A
master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been clocked out of the slave. In this case, the slave
must leave the data line high to enable the master to
generate the stop condition.
Data transfer from a master transmitter to a slave
receiver. The first byte transmitted by the master is the
command/control byte. Next follows a number of data
bytes. The slave returns an acknowledge bit after each
received byte.
Data transfer from a slave transmitter to a master
receiver. The master transmits the first byte (the com-
mand/control byte) to the slave. The slave then returns
an acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The mas-
ter returns an acknowledge bit after all received bytes
other than the last byte. At the end of the last received
Hex Nonvolatile Potentiometer with
I/O and Memory
Figure 4. Slave Address
10
_____________________________________________________________________
MSB
1
IDENTIFIER
DEVICE
0
1
0
A2
ADDRESS
DEVICE
A1
A0
R/W
LSB
byte, a not acknowledge can be returned.
The master device generates all serial clock pulses and
the start and stop conditions. A transfer is ended with a
stop condition or with a repeated start condition. Since
a repeated start condition is also the beginning of the
next serial transfer, the bus is not released.
The DS3930 can operate in the following three modes:
1)
2)
3)
Following the start condition, the DS3930 monitors the
SDA bus checking the device type identifier being
transmitted. Upon receiving the 1010 device identifier,
the appropriate device address bit, and the read/write
bit, the slave device outputs an acknowledge signal on
the SDA line.
Slave Receiver Mode: Serial data and clock are
received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is trans-
mitted. Start and stop conditions are recognized as
the beginning and end of a serial transfer. Address
recognition is performed by hardware after the
slave (device) address and direction bit have been
received.
Slave Transmitter Mode: The first byte is received
and handled as in the slave receiver mode.
However, in this mode the direction bit indicates
that the transfer direction is reversed. Serial data is
transmitted on SDA by the DS3930 while the serial
clock is input on SCL. Start and stop conditions are
recognized as the beginning and end of a serial
transfer.
Slave Address: This is the first byte received fol-
lowing the start condition from the master device.
The slave address consists of a 4-bit control code.
For the DS3930, this is set as 1010 binary for
read/write operations. The next bits of the slave
address are the device address (A2–A0). The last
bit of the slave address (R/W) defines the operation
to be performed. When set to a ‘1,’ a read operation
is selected, and when set to a ‘0,’ a write operation
is selected (see Figure 4).