DS3930 Maxim Integrated Products, DS3930 Datasheet - Page 9

• Manufacturer Part Number: DS3930
• Description: DS3930 Hex Nonvolatile Potentiometer With I/o And Memory
• Manufacturer: Maxim Integrated Products

Figure 2. I/O Cell
The 2-wire serial port interface supports a bidirectional
data transmission protocol with device addressing. A
device that sends data on the bus is defined as a trans-
mitter, and a device receiving data as a receiver. The
device that controls the message is called a “master.”
The devices that are controlled by the master are
“slaves.” The bus must be controlled by a master
device that generates the serial clock (SCL), controls
the bus access, and generates the start and stop con-
ditions. The DS3930 operates as a slave on the 2-wire
bus. Connections to the bus are made through the
open-drain I/O lines, SDA and SCL. The following I/O
terminals control the 2-wire serial port: SDA, SCL, and
A0. Timing diagrams for the 2-wire serial port can be
Figure 3. 2-Wire Data Transfer Protocol
SDA
SCL
PULLUP
CONDITION
CTRL
START
2-Wire Serial Port Operation
SETTING
I/O PIN
INPUT
MSB
1
2
SLAVE ADDRESS
Hex Nonvolatile Potentiometer with
V
6
CC
_____________________________________________________________________
ESD
R
I/O
7
DIRECTION
I/O
R/W
BIT
8
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
ACK
9
found in Figures 3 and 5. Timing information for the 2-
wire serial port is provided in the AC Electrical
Characteristics table for 2-wire serial communications.
The following bus protocol has been defined:
•
•
Accordingly, the following bus conditions have been
defined:
Bus Not Busy: Both data and clock lines remain high.
Start Data Transfer: A change in the state of the data
line from high to low while the clock is high defines a
start condition.
Stop Data Transfer: A change in the state of the data
line from low to high while the clock line is high defines
the stop condition.
Data Valid: The state of the data line represents valid
data when, after a start condition, the data line is stable
for the duration of the high period of the clock signal. The
data on the line can be changed during the low period of
the clock signal. There is one clock pulse per bit of data.
Figures 3 and 5 detail how data transfer is accomplished
on the 2-wire bus. Depending upon the state of the R/W
bit, two types of data transfer are possible.
Each data transfer is initiated with a start condition and
Data transfer can be initiated only when the bus is
not busy.
During data transfer, the data line must remain sta-
ble whenever the clock line is high. Changes in the
data line while the clock line is high are interpreted
as control signals.
1
2
REPEATED IF MORE BYTES
ARE TRANSFERRED
I/O and Memory
3–7
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
8
ACK
9
OR REPEATED
CONDITION
CONDITION
START
STOP
9