SDA9380 Micronas Intermetall GmbH, SDA9380 Datasheet
SDA9380
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SDA9380 Summary of contents
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Edition May 3, 2001 6251-549-2PD PRELIMINARY DATA SHEET SDA 9380-B21 EDDC Enhanced Deflection Controller and RGB Processor ...
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SDA 9380 - B21 Document Change Note 1 DS Date Page 2 31.03.98 Version 02 3 17.07.98 Document state 03 corresponds to silicon version A11 23.07.98 3 block diagram changed 23.07.98 46 bandwidth of YUV increased (new value 30 MHz) ...
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SDA 9380 - B21 1 DS Date Page 24.03.99 46 DAC output D/A: DNL changed from +-0.5 LSB to +-1 LSB 29.03.99 22 IIC bus: ABLTCS1, 0 added 29.03.99 25 IIC bus: GAIN2 added, MODE changed 30.03.99 26 IIC bus: ...
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SDA 9380 - B21 1 DS Date Page 30.06.99 30 Equations of Horizontal and AFC EHT compensation changed 09.07.99 38, 39 Minimum ambient temperature at operating changed from - °C 09.07.99 21 Bit position 6 of PLL control ...
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SDA 9380 - B21 1 DS Date Page 25.08.00 49 Nominal brightness and measurement levels changed 28.08.00 44 Black stretch level shift changed 28.08.00 50 Foot note 1) added 04.10.00 38 Absolute maximum rating of VDD(MC 04.10.00 38 ...
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SDA 9380 - B21 Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irre- versible damage to the integrated circuit. Recommended Operating Conditions Under this conditions the functions given in the circuit ...
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SDA 9380 - B21 Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SDA 9380 - B21 11.6 Black Stretch diagram ...
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SDA 9380 - B21 1 General description The SDA 9380 is a highly integrated deflection controller and RGB video processor for CTV receiv- ers with 15 to 19kHz 38kHz line frequencies. The deflection component controls among oth- ...
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SDA 9380 - B21 =Protection against EHT run away (X-rays protection) =Protection against missing V-deflection (CRT-protection) =D/A ouput with 8 bit resolution for general purpose =Digital output for general purpose, controlled by I =Selectable softstart of the H-output stage 2.2 ...
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SDA 9380 - B21 3 Block diagram SWITCH D/A SCL SDA BSOIN RESN TEST CONTROL FH1_2 VSYNC HSYNC CLEXT CLKI HSAFE H35K H38K X1 X2 RGB 2 CLAMP 3 FBL 2 FBL 1 CLAMP 3 CLAMP 3 BRIGHTNESS CONTROL VDD(A1..4) ...
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SDA 9380 - B21 4 Pin configuration CLKI CLEXT 5 TEST 6 SUBST 7 RESN 8 SCL 9 SDA 10 VDD(D) 11 ...
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SDA 9380 - B21 4.1 Pin description Pin No. Name 1 CLKI CLEXT 5 TEST 6 SUBST 7 RESN 8 SCL 9 SDA 10 VDD(D) 11 VSS( H35K 14 H38K 15 PWM ...
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SDA 9380 - B21 Pin No. Name 36 VREFH 37 VBLO 38 VREFN 39 VREFC 40 DCI 41 VDD(A4 VSS(A4 ...
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SDA 9380 - B21 5 System description 5.1 Functional description 5.1.1 Deflection controller The main input signals are HSYNC with a frequency range of about 31 to 38kHz and VSYNC with vertical frequencies 120 Hz. When connecting ...
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SDA 9380 - B21 within 85ms to its final value. The high time is kept constant. The normal operating pulse ratio H/L is either 45/55 or 40/60 (selectable by I²C). A watch dog function limits an increasing of the HD ...
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SDA 9380 - B21 BG-pulse width t b Delay to HSYNC t db Micronas 54 / CLL internal clock: (78-4*Internal_H-sync_phase)/ CLL external clock: (38-4*Internal_H-sync_phase)/ CLL 5-9 Preliminary Data Sheet System description 2001-05-03 ...
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SDA 9380 - B21 5.1.2 RGB processing To provide an accurate biasing of the picture tube the offsets and gains of the RGB output stages are continuously adjusted by a cut off and white level control loop. Leakage, cut off ...
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SDA 9380 - B21 5.2 Circuit description The HSYNC is reference for a numeric PLL. This PLL generates a clock which is phase locked to the incoming horizontal sync pulse and exactly 864 times faster than the horizontal frequency. The ...
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SDA 9380 - B21 Once an increment has been obtained, either from the PI-filter or the I operate the Digital Timing Oscillator. The DTO generates a saw-tooth with a frequency that is pro- portional to the increment. The saw-tooth is ...
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SDA 9380 - B21 5.3 Reset modes The circuit is only completely reset at power-on/off (timing diagram ref. 11.3). If the pin RESN has L- level or during standby operation some parts of the circuit are not affected (timing diagram ...
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SDA 9380 - B21 I : interlaced NI : non interlaced If NSA = 0 (subaddr. 01/D5) number of lines per field is selfadaptable between 192 and 680 for each specified H-frequency. 5.5 I²C-Bus control 5.5.1 I²C-Bus address 5.5.2 I²C-Bus ...
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Sub- Control item addr. (for deflection) Deflection control 0 00 Deflection control 1 01 Vertical scroll *) Vertical aspect *) Vertical shift *) Vertical size *) B7 B6 ...
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Sub- Control item addr. (for RGB) RGB control 0 1F RGB control 1 20 RGB control 2 21 Video input mode 22 Brightness 23 Contrast 24 Saturation 25 Average beam current limit *) 26 Average beam current limit characteristics 27 ...
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SDA 9380 - B21 At power on most of the data are zero by default (if not otherwise specified) before transferring indi- vidual values via IIC-bus. Allowed values out of the effective range are limited, e.g. Internal H-sync phase =127 ...
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SDA 9380 - B21 5.5.4 Detailed description The Deflection control byte 0 includes the following bits: VOFF STDBY - VOFF: Vertical off 0: normal vertical output due to control items 1: vertical saw-tooth is switched off, vertical protection is disabled ...
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SDA 9380 - B21 The Deflection control byte 1 includes the following bits: BSO1 BSO0 - BSO1.. BSO0 Black Switch-Off behaviour 00: no Black Switch-Off 01: Black Switch-Off mode 1 (see section 11.2) 10: Black Switch-Off mode 2 (see section ...
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SDA 9380 - B21 The Vertical sync control byte includes the following bits SSC: Sandcastle without VBL 0: output SCP with VBL component 1: output SCP without VBL component - NI: Non interlace 0: interlace depends on ...
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SDA 9380 - B21 The PLL control byte 0 includes the following bits -INCR4..0: Nominal PLL output frequency INCR=INT((FH*55296)/FQ-64.625) (for typical values see table below) specified range:6 INCR (FQ=24.576MHz) Application PAL (50Hz) NTSC (60Hz) PAL (60Hz) PAL (100Hz) ...
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SDA 9380 - B21 - NOISYVCR:Handling of noisy input signals in VCR mode 0: normal handling 1: improved handling Note: this bit is don’t care if bit VCR = 0 (TV mode) - HSWMI: Minimum width of HSYNC 0: 1.5µs ...
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SDA 9380 - B21 The RGB control byte 0 includes the following bits: IN2NOM IN1NOM - IN2NOM: Nominal saturation and contrast for video input 2 0: variable saturation and contrast for video input 2 (defined by reg. 24, 25) 1: ...
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SDA 9380 - B21 The RGB control byte 1 includes the following bits: BLUES SLBLKS - BLUES: Blue stretch 0: off SLBLKS: Slow Black stretch 0: short time constant 1: long time constant - BLCKS: Black stretch ...
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SDA 9380 - B21 - COR1..0: Contrast reduction of the channel 0 and 1 at FBL2 DELOFF:Delay from SVM output to RGB output 0: delay on (see ...
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SDA 9380 - B21 - YLL: Y0 input low level for PAL and NTSC matrices (black-to-white value) 1: 0.7 V (black-to-white value) The Average beam current limit characteristics includes the following bits: GAIN2 GAIN1 - GAIN2..0: Gain ...
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SDA 9380 - B21 The Peak drive limit register includes the following bits: PDLIM3 PDLIM2 - PDLIM3..0: Peak drive limit 1000: minimum level ... 0000: default level ... 0111: maximum level - PDLT1..0: Peak drive limiter time constant 10: faster ...
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SDA 9380 - B21 The Status byte includes the following bits: HPON VPON - HPON: H-protection on 0: normal operation of the line output stage 1: upper threshold on input HPROT has been exceeded *) - VPON: V-protection on 0: ...
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SDA 9380 - B21 5.5.5 Explanation of some control items Vertical aspect, Two special control items are implemented for the user to adjust the Vertical scroll: vertical height (control item: Vertical aspect) and the vertical position (Vertical scroll). These items ...
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SDA 9380 - B21 V If Vertical EHT compensation = -128 the outputs VD+ and VD- are independent of the input signal IBEAM. Horizontal EHT comp.:This item controls the influence of the input signal IBEAM on the output E/W according ...
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SDA 9380 - B21 Vertical blanking start (VBS), RGB ref. pulse pos. (RPP), Vertical blanking end (VBE): The control item RPP defines the position of the three reference pulses for Red ref. pulse Green ref. pulse = ...
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SDA 9380 - B21 HSYNC VSYNC 1 line VD- start of odd field VBL (default: BSE=0, VBS=0, VBE=0) 2 lines VBL (BSE=0, VBS=2, VBE=0) VBL (BSE=1, RPP=1, VBS=0, VBE =1) Internal v ertical blanking pulse VBL when JMP = 0 ...
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SDA 9380 - B21 A HSYNC 1 VSYNC 1 line VD- start of odd field VBL (default: BSE=0, VBS=0) 2 lines VBL (BSE=0, VBS=2) VBL (BSE=0, VBS=0, VBE=1) Internal vertical blanking pulse VBL when JMP = 1 and number of ...
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SDA 9380 - B21 Min. No. of lines / field: It defines the minimum number of lines per field for the vertical synchroniza- tion. If the TV standard at the inputs VSYNC and HSYNC has less lines per field than ...
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SDA 9380 - B21 Peak dark detection (PDD) top border, bottom border, left border, right border: These four control items define the picture area insides the peak dark detector is enabled. The peak dark detector is storing the lowest level ...
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SDA 9380 - B21 White control R, white control G, white control B, CATH[2:0]: These four control items define the nominal values of the cut-off and white- drive currents during the measurement lines. They can be calculated with the following ...
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Mode Description Characteristics normal mode RGB ref. pulse position = line 20... 22 (odd field) N0 (for 4:3 source, Letterbox) end of V-blanking = line 22 (odd field) with default settings guard band = 1.5 lines normal mode RGB ref. ...
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Mode Description Characteristics normal mode RGB ref. pulse position = line 20... 22 (odd field) N0 (for 16:9 or 4:3 source) end of V-blanking = line 22 (odd field) with default settings guard band = 1.5 lines normal mode RGB ...
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SDA 9380 - B21 6 Pin schematic pin ROUT, GOUT, BOUT SCP HD Micronas schematic PAD ESD protection PAD ESD protection ESD protection PAD 6-39 Preliminary Data Sheet Pin schematic remark bipolar output stage, supply voltage: V DD(MC) bipolar output ...
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SDA 9380 - B21 pin X1, X2 PAD X2 PAD X1 SVM CLKI, CLEXT, TEST, RESN, SCL, SDA, H35K, H38K, PWM, VSYNC, FH1_2, HSYNC, PHI2, PROTON, VBLO, FBL1, FBL2, SWITCH Micronas schematic ESD protection ESD protection PAD ESD protection PAD ...
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SDA 9380 - B21 pin E/W, D/A, VD+, VD-, VPROT, HPROT, HSAFE, BSOIN, IBEAM, VREFH, PAD VREFN, VREFC, DCI, Y/R0, U/G0, V/B0, Y/R1, U/G1, V/B1, R2, G2, B2 Micronas schematic ESD protection ESD protection 6-41 Preliminary Data Sheet Pin schematic ...
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SDA 9380 - B21 7 Absolute maximum ratings Parameter Operating temperature Storage temperature Junction temperature Soldering temperature Input voltage Input voltage Output voltage Supply voltages Supply voltage Supply total voltage difference VSS, SUBST total voltage difference Total power dissipation Latch-up ...
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SDA 9380 - B21 8 Recommended operating conditions Parameter Supply voltages Supply voltage Ambient temperature 1 ) Any sequence and any rise time of the 3.3V and 8V supply voltage is allowed at power on. But all VSS pins as ...
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SDA 9380 - B21 Parameter Input voltage when watching of HSAFE is disabled Input IBEAM Low input voltage Full range input voltage Reference Voltage Pins VREFH voltage VREFN voltage VREFC resistor to VREFN Input 2 Low-level input voltage High-level input ...
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SDA 9380 - B21 Parameter Input VSYNC Pulse width high Pulse width high Pulse width high Input CLKI (external clock mode, CLEXT=high) Input frequency Quartz Oscillator Input / Output X1, X2 Crystal frequency Crystal resonant impedance External capacitance YUV Inputs ...
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SDA 9380 - B21 Parameter Maximum input current during clamping Internal bias during clamping Difference between black level of internal and external signals at the outputs Delay difference of the three channels Fast Blanking Input FBL1 (RGB/YUV 1) Input voltage ...
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SDA 9380 - B21 Parameter Input voltage data insertion Dark current input DCI for cut off and white level control Low input voltage Full range input voltage Maximum input current Input RGB matrices PAL/SECAM mode RGB matrix coefficients ...
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SDA 9380 - B21 Parameter Saturation control (control bit B0...B5; subaddress 25h) Saturation control range Nominal saturation B7...B2 = 110001 Contrast control (control bit B7...B0; subaddress 24h) Contrast control range Nominal contrast B7...B0 = 00000000 Tracking between the three channels ...
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SDA 9380 - B21 Parameter Slope IIC bus: peak drive limit B1, Blue stretch (control bit BLUES; subaddress 20h) Decrease of small signal gain for red and green at nominal input amplitu- des and nominal settings ...
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SDA 9380 - B21 Characteristics (assuming recommended operating conditions) 9 Characteristics (assuming recommended operating conditions) Parameter Average supply current DD(D) DD(A1..4) Average supply current of V DD(MC) Total power dissipation Standby supply current DD(D) ...
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SDA 9380 - B21 Characteristics (assuming recommended operating conditions) Parameter Output PWM Output Low level Output High level Period Resolution Output SCP Output Low level Output BLanking level Output High level DAC Output D/A DAC Resolution DAC Output LOW DAC ...
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SDA 9380 - B21 Characteristics (assuming recommended operating conditions) Parameter Gain error INL DNL *) input range = 100...900 DAC Output VD+, VD- DAC resolution DAC output LOW (VD-) DAC output HIGH (VD-) DAC output LOW (VD-) - (VD+) DAC ...
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SDA 9380 - B21 Characteristics (assuming recommended operating conditions) Parameter Delay from positive-going threshold output HSYNC Delay from negative-going threshold output HSYNC Output H38K Output Low level Output High level Positive-going threshold of f ...
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SDA 9380 - B21 Characteristics (assuming recommended operating conditions) Parameter Variation of black level with 1) temperature Gain range of white point control loop Relative variation in black level bet- ween all inputs during variation of: 1) Supply voltage (+-10%) ...
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SDA 9380 - B21 10 Application information 10.1 System overview Dig. TV 100Hz CVBS1 CVBS7 RGB1 RGB2 10.2 System overview Multisync Deflection SCP 15pF X1 24,576 MHz X2 15pF VSYNC HSYNC Micronas Y U VSP 9402 V Processor, PRIMUS Deflection ...
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SDA 9380 - B21 10.3 Application circuit diagram VSYNC HSYNC 27k +3.3 V 100n YUV RGBFB1 RGBFB2 CLK IIC bus Micronas +3.3 V +3.3 V +3.3 ...
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SDA 9380 - B21 11 Waveforms 11.1 Timing diagram of H35K and H38K kHz HSYNC kHz H H35K H38K 11.2 Black Switch-Off diagrams BSOIN VBL com- ponent of SCP VD+ ROUT, BOUT, ...
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SDA 9380 - B21 Mode 1 (constant overscan, BSO = 01): V-overscan = f (voltage at BSOIN) 160 152 144 136 128 120 112 104 Mode 2 (parabolic function, BSO = 10): V-overscan = ...
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SDA 9380 - B21 11.3 Power On/Off diagram max. 2.6V Supply Voltage Power- On- Reset 32768 cycles X1 C-Bus tristate VREFH Protection active (HPROT inactive >1.5V C-Reg. de- fault 00, 1D..30h 2 I C-Reg. ...
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SDA 9380 - B21 11.4 Standby mode, RESN diagram Standby RESN HD Phi2-loop active CPU inactive active VREFH inactive active Protection (HPROT inactive >1.5V C-Reg. programmable 01.. C-Reg. 00, 1D..30h Micronas ~ 42 CLL cycles Phi2-loop ...
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SDA 9380 - B21 11.5 Function of H,V protection HPROT 2/f ...3 64 depends on IIC control items b) HPON ...
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SDA 9380 - B21 11.6 Black Stretch diagram 100 50 -30 11.7 Soft Clipping diagram Micronas 0 50 maximum black stretch 11-62 Preliminary Data Sheet Waveforms 100 Input ...
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SDA 9380 - B21 12 Package outlines P-MQFP-64 Micronas Preliminary Data Sheet 12-63 Package outlines 2001-05-03 ...
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SDA 9380-B21 Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-549-2PD 72 PRELIMINARY DATA SHEET All information and data contained in this ...