SDA9380 Micronas Intermetall GmbH, SDA9380 Datasheet - Page 16

• Manufacturer Part Number: SDA9380
• Description: Enhanced Deflection Controller And RGB Video Processor (EDDC)
• Manufacturer: Micronas Intermetall GmbH

SDA 9380 - B21
within 85ms to its final value. The high time is kept constant. The normal operating pulse ratio H/L is
either 45/55 or 40/60 (selectable by I²C). A watch dog function limits an increasing of the HD period
to max. +10%.
The implemented Black Switch-Off behaviour is defined by two I
enabled the signal at BSOIN (e.g. the supply voltage of the line output stage) is watched. If its level
does not come up to a defined threshold Black Swich-Off is started (see 11.2). At first the RGB out-
puts are switched to continuous blanking immediately and the vertical output signals are changed to
about 115..120% overscan. After a delay of 42 lines the picture tube capacitance is discharged with
a current of some mA. From now the vertical overscan rate is calculated depending on the actual
voltage at BSOIN to get the desired deflection angle. Three relations are selectable by I
voltage at BSOIN is dropped down to about 20% of its initial value the output HD and the overscan
calculation may stop.
The protection circuit watches an EHT reference and the saw-tooth of the vertical output stage. If
the EHT succeeds a defined threshold or if the V-deflection fails (refer to 11.5) the related bit is set in
the status byte and the output PROTON goes High. The output HD is deactivated (H-level) immedi-
ately independent of the selected Black Switch-Off function.
HPROT:
VPROT:
The pin SCP delivers the composite blanking signal SCP. It contains burst (V
(V
can be varied by I
Micronas
HBL
) and selectable V-blanking (control bit SSC). The phase and width of the H-blanking period
BD = 1
BD = 0, BSE = 0 (default value)
BD = 0, BSE = 1(alignment range)
SSC = 0
SSC = 1
input V
vertical saw-tooth voltage
V
or V
i
< V1 in first half of V-period
i
2
> V2 in second half : HD disabled
C-Bus. For the timing following settings are possible :
V
V2 = V
i
i
< V2
> V1
i
< V1
continuous blanking
HD disabled
operating range
5-8
: T
: T
: T
: T
: T
: T
BL
HBL
HBL
DBL
BL
BL
= 0
= T
is always T
= t
= (4 * H_blanking-time + 1) / CLL
= (H_shift + 4 * H_blanking_phase
VBL
- 2*H_blanking_time + 45) / CLL
f
(H-flyback time)
during V-blanking period
HBL
2
C bits (BSO1, BSO0). When
Preliminary Data Sheet
System description
b
), H-blanking HBL
2
2001-05-03
C. After the