PIC16CR58A Microchip Technology, PIC16CR58A Datasheet - Page 28

• Manufacturer Part Number: PIC16CR58A
• Description: ROM-Based 8-Bit CMOS Microcontroller Series
• Manufacturer: Microchip Technology

PIC16C6X
TABLE 4-4:
DS30234D-page 28
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h-1Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Note 1: These registers can be addressed from either bank.
Address Name
Bank 0
(1)
(1)
(1)
(1)
(1,2)
(1)
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The BOR bit is reserved on the PIC16C64, always maintain this bit set.
5: The IRP and RP1 bits are reserved on the PIC16C64/64A/R64, always maintain these bits clear.
6: PIE1<6> and PIR1<6> are reserved on the PIC16C64/64A/R64, always maintain these bits clear.
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter. (PC<12:8>)
—
—
SPECIAL FUNCTION REGISTERS FOR THE PIC16C64/64A/R64
Unimplemented
Unimplemented
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
Timer2 module’s register
Synchronous Serial Port Receive Buffer/Transmit Register
Capture/Compare/PWM1 (LSB)
Capture/Compare/PWM1 (MSB)
WCOL
PSPIF
IRP
Bit 7
GIE
—
—
—
—
—
—
(5)
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
SSPOV
RP1
Bit 6
PEIE
(6)
—
—
—
—
—
(5)
PORTA Data Latch when written: PORTA pins when read
T1CKPS1
SSPEN
CCP1X
Bit 5
T0IE
RP0
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
T1CKPS0 T1OSCEN
CCP1Y
Bit 4
INTE
CKP
TO
—
—
CCP1M3
SSPM3
SSPIF
RBIE
Bit 3
PD
—
TMR2ON
CCP1M2
T1SYNC
CCP1IF
SSPM2
Bit 2
RE2
T0IF
Z
T2CKPS1 T2CKPS0 -000 0000 -000 0000
TMR1CS
CCP1M1
TMR2IF
SSPM1
Bit 1
INTF
RE1
DC
TMR1ON
CCP1M0
TMR1IF
SSPM0
Bit 0
RBIF
RE0
1997 Microchip Technology Inc.
C
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--xx xxxx --uu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
00-- 0000 00-- 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
Value on:
POR,
BOR
—
—
Value on
all other
resets
—
—
(3)