MT5C1008 ASI, MT5C1008 Datasheet - Page 5

• Manufacturer Part Number: MT5C1008
• Description: 128K x 8 SRAM WITH DUAL CHIP ENABLE AVAILABLE AS MILITARY SPECIFICATIONS
• Manufacturer: ASI

NOTES
1.
2.
3.
4.
5.
6.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
MT5C1008
Rev. 6.5 7/02
V
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
CC
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
All voltages referenced to V
-2V for pulse width < 20ns
I
The specified value applies with the outputs
unloaded, and f =
This parameter is guaranteed but not tested.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
are specified with CL = 5pF as in Fig. 2. Transition is
measured ±200mV typical from steady state voltage,
allowing for actual tester RC time constant.
LZCE,
CC
for Retention Data
DESCRIPTION
is dependent on output loading and cycle rates.
t
LZWE,
CE1\
CE2
t
LZOE,
V
t
Austin Semiconductor, Inc.
RC (MIN)
CC
1
V
V
V
V
t
IL
IL
IH
IH
HZCE,
1 2 3 4 5 6 7 8 9
1 2 3
1 2 3 4
1 2 3 4 5 6 7 8 9
1 2 3
1 2 3 4
1 2 3 4 5 6 7 8 9
1 2 3
1 2 3 4
1 2 3 4 5 6 7 8 9
1 2 3
1 2 3 4
1 2 3 4 5 6 7 8 9
1 2 3
1 2 3 4
1 2 3 4 5 6 7 8 9
1 2 3
1 2 3 4
1 2 3 4 5 6 7 8 9
1 2 3
1 2 3 4
1 2 3 4 5 6 7 8 9
1 2 3
1 2 3 4
SS
Hz.
(GND).
CE\ > (V
V
LOW Vcc DATA RETENTION WAVEFORM
IN
or < 0.2V, f=0
t
HZOE and
> (V
t
CONDITIONS
CDR
CC
CC
- 0.2V)
- 0.2V)
t
HZWE
4.5V
DATA RETENTION MODE
V
<V
CC
V
V
5
SS
DR
DR
= 2V
7.
8.
9.
10. Address valid prior to, or coincident with, latest
11.
12. CE2 timing is the same as CE1\ timing. The
13. Chip enable (CE1\, CE2) and write enable (WE\) can
+ 0.2V
> 2V
Q
255
At any given temperature and voltage condition,
t
t
WE\ is HIGH for READ cycle.
Device is continuously selected. Chip enables and
output enables are held in their active state.
occurring chip enable.
t
waveform is inverted.
initiate and terminate a WRITE cycle.
HZCE is less than
LZWE and
RC = Read Cycle Time.
Fig. 1 Output Load
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
SYMBOL
I
Equivalent
CCDR
t
V
CDR
t
DR
R
4.5V
t
HZOE is less than
+5V
t
R
MIN
t
t
LZCE, and
RC
2
0
480
30
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Q
MAX
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
255
1.0
---
---
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3
t
t
LZOE.
HZWE is less than
MT5C1008
Fig. 2 Output Load
1 2 3
1 2 3
1 2 3
1 2 3
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
UNITS NOTES
mA
Equivalent
SRAM
SRAM
SRAM
ns
ns
SRAM
SRAM
V
UNDEFINED
DON’T CARE
+5V
4, 11
480
5 pF
4