RS2051 Orister Corporation, RS2051 Datasheet - Page 7

• Manufacturer Part Number: RS2051
• Description: Green?mode
• Manufacturer: Orister Corporation

OLP & SCP
To protect the circuit from being damaged under the over load or short circuit condition, a smart OLP&SCP function is
implemented in the RS2051. When short circuit or over load occurs in the output end, the feedback cycle would enhance the
voltage of FB pin, while the voltage is over 3.7V or the current from FB is below 170uA, the internal detective circuit would
send a signal to shut down the GATE and pull down the VDD voltage, then the circuit is restart. To avoid the wrong operation
when circuit starts, the delay time is set. When the RI resistance is 100Kohm, the delay time T
50ms. The relationship between RI and T
Anti Intermission Surge
When the power supplies change the heavy load to light load immediately, there could be tow phenomena caused by system
delay. They are output voltage overshot and intermission surge. To avoid it, the anti intermission surge is built in the RS2051.
If it occurs, the FB current is to increase rapidly, the GATE would be cut off for a while, VDD pin voltage descends gradually.
When VDD reaches 9.4V, the GATE pin would operate again, which the frequency is 22KHz.
Leading‐edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn‐on spike will inevitably occur at the Sense pin, which would disturb the
internal signal from the sampling of the R
turn‐on spike, and the power MOSFET cannot be switched off during the moment. So that the conventional external RC
filtering on sense input is no longer required.
OVP
There is a 25.6V over‐voltage protection circuit in the RS2051 to improve the credibility and extend the life of the chip. When
the VDD voltage is over 25.6V, the GATE pin is to shutdown immediately and the VDD voltage is to descend rapidly.
GATE Driver & Soft Clamped
The RS2051 output designs a totem pole to drive a periphery power MOSFET. The dead time is introduced to minimize the
transfixion current during the output operating. The novel soft clamp technology is introduced to protect the periphery
power MOSFET from breaking down and current saturation of the Zener.
DS‐RS2051‐09 November, 2009
OLP&SCP
SENSE
6
. There is a 300ns leading edge blanking time built in to avoid the effect of the
RI
follows the below equation.
×
×
10
2
3
(
ms
< )
T
OLP
&
SCP
<
6
RI
×
×
10
3
3
(
ms
)
OLP&SCP
is between 33ms and
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