10EL34 ON Semiconductor, 10EL34 Datasheet

10EL34

Manufacturer Part Number

10EL34

Description

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Datasheet

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Generation Chip

designed explicitly for low skew clock generation applications. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned. The device can be driven by either

a differential or single-ended ECL or, if positive power supplies are used,

PECL input signal. In addition, by using the V BB output, a sinusoidal

source can be AC coupled into the device (see Interfacing section of the

ECLinPS Data Book DL140/D). If a single-ended input is to be used, the

V BB output should be connected to the CLK input and bypassed to ground

via a 0.01 F capacitor. The V BB output is designed to act as the switching

reference for the input of the EL34 under single-ended input conditions,

as a result, this pin can only source/sink up to 0.5mA of current.

will only be enabled/disabled when the internal clock is already in the

LOW state. This avoids any chance of generating a runt clock pulse on

the internal clock when the device is enabled/disabled as can happen

with an asynchronous control. An internal runt pulse could lead to losing

synchronization between the internal divider stages. The internal enable

flip-flop is clocked on the falling edge of the input clock, therefore, all

associated specification limits are referenced to the negative edge of the

clock input.

master reset (MR) input allows for the synchronization of the internal

dividers, as well as multiple EL34s in a system.

12/93

Motorola, Inc. 1996

50ps Output-to-Output Skew

Synchronous Enable/Disable

Master Reset for Synchronization

75k Internal Input Pulldown Resistors

>1000V ESD Protection

The MC10/100EL34 is a low skew 2, 4, 8 clock generation chip

The common enable (EN) is synchronous so that the internal dividers

Upon startup, the internal flip-flops will attain a random state; the

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

V CC

8 Clock

V CC

CLK

3–1

V BB

V CC

V EE

REV 2

CLK

Z = Low-to-High Transition

ZZ = High-to-Low Transition

CLK

V BB

Q 0

Q 1

Q 2

MC100EL34

MC10EL34

PLASTIC SOIC PACKAGE

PIN DESCRIPTION

FUNCTION TABLE

CASE 751B-05

FUNCTION

Diff Clock Inputs

Sync Enable

Master Reset

Reference Output

Diff 2 Outputs

Diff 4 Outputs

Diff 8 Outputs

D SUFFIX

FUNCTION

Divide

Hold Q 0–3

Reset Q 0–3

Related parts for 10EL34

10EL34 Summary of contents

Page 1

... 3–1 MC10EL34 MC100EL34 SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 PIN DESCRIPTION PIN FUNCTION CLK Diff Clock Inputs EN Sync Enable MR Master Reset V BB Reference Output Q 0 Diff 2 Outputs Q 1 Diff 4 Outputs ...

Page 2

... MC10EL34 MC100EL34 AC/DC CHARACTERISTICS ( (min (max GND) Symbol Characteristic f MAX Max Toggle Frequency I EE Power Supply Current 100EL V BB Output Reference 10EL Voltage 100EL I IH Input High Current t PLH Propagation CLK Q0 t PHL Delay to CLK Q1,2 Output MR Q www.DataSheet4U.com ...

Page 3

... Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 3–3 MC10EL34 MC100EL34 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. ...

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