S2078TB Applied Micro Circuits Corporation, S2078TB Datasheet - Page 7

• Manufacturer Part Number: S2078TB
• Description: DUAL FIBRE CHANNEL TRANSCEIVER
• Manufacturer: Applied Micro Circuits Corporation

RECEIVER DESCRIPTION
Each receiver channel is designed to implement the
ANSI X3T11 Fibre Channel specification. A block
diagram showing the basic function is provided in
Figure 4.
Whenever a signal is present, the receiver attempts
to recover the serial clock from the received data
stream. After acquiring bit synchronization, the
S2078 searches the serial bit stream for the occur-
rence of a K28.5 character on which to perform word
synchronization. Once synchronization on both bit
and word boundaries is achieved, the receiver pro-
vides the word-aligned data on its parallel outputs.
Data Input
A differential input receiver is provided for each
channel of the S2078. Each channel has a loopback
mode in which the serial data from the transmitter
replaces external serial data. The loopback function
for the two channels is controlled by the loopback
enable signal, LPEN.
The high speed serial inputs to the S2078 are inter-
nally biased to VDD–1.3V. This facilities AC-coupling
of the differential inputs and termination with a single
differential termination.
Clock Recovery Function
Clock recovery is provided for each channel of the
S2078. The receiver PLL has been optimized for the
needs of Fibre Channel systems. A simple state ma-
chine in the clock recovery macro decides whether to
acquire lock from the serial data input or from the
reference clock. The decision is based upon the fre-
quency and run length of the serial data inputs.
October 13, 2000 / Revision D
DUAL FIBRE CHANNEL TRANSCEIVER
The run-length requirements insure that the S2078
will respond appropriately and quickly to a loss of
signal. The run-length checker looks for a minimum
of 120 consecutive ones or zeros. The checking is
done in parallel, thus 12 parallel words are examined.
An off-frequency detection circuit in the S2078 moni-
tors the receiver VCO frequency to insure that the
input signal is at a valid data rate. The data stream
must be within 200 ppm of the appropriate rate for
reliable locking of the CRU to the data stream.
If both the off-frequency test and the run-length test
are satisfied, the CRU will attempt to lock to the
incoming data. Note that if the run length test is sat-
isfied due to noise on the inputs, and no signal is
present, the receiver VCO will maintain frequency
accuracy to within 100 ppm of the target rate as
determined by the REFCLK.
In any transfer of PLL control from the serial data to
the reference clock, the RBC1/0x outputs remain
phase continuous and glitch free, assuring the integ-
rity of downstream clocking.
If at any time, the frequency or run length checks are
violated, the state machine forces the VCO to lock to
the reference clock. This is required to guarantee
that the VCO maintains the correct frequency in the
absence of data.
Reference Clock Input
The reference clock must be provided from a low jitter
clock source. The frequency of the received data
stream (divided by 10 or 20) must be within 200 ppm
of the reference clock to insure reliable locking of the
receiver PLL. A single reference clock is provided to
both the transmitter and the receiver of the S2078.
S2078
7