ACS8525T Semtech, ACS8525T Datasheet - Page 22

• Manufacturer Part Number: ACS8525T
• Description: Line Card Protection Switch for SONET/SDH Systems
• Manufacturer: Semtech

Outputs
The ACS8525 delivers four output signals on the following
ports: Two clocks, one each on ports Output O1 and
Output O2; and two Sync signals, on ports FrSync and
MFrSync. Output O1 and Output O2 are independent of
each other and are individually selectable. Output 01 is a
differential port (pins O1POS and O1NEG), and can be
selected PECL or LVDS. Output O2 (pin O2) and the Sync
outputs are TTL/CMOS.
The two Sync outputs, FrSync (8 kHz) and MFrSync
(2 kHz), are derived from DPLL1.
PECL/LVDS Output Port Selection
The choice of PECL or LVDS compatibility for Output 01 is
programmed via the cnfg_differential_output register,
Reg. 3A.
Output Frequency Selection and PLL Configuration
The output frequency at many of the outputs is controlled
by a number of inter-dependent parameters (refer to “PLL
Architecture” on page 14). The frequencies of the output
Table 6 Output Reference Source Selection Table
Note...1.544 MHz/2.048 MHz are shown for SONET/SDH respectively. Pin SONSDHB controls default, when High SONET is default
Table 7 Output Frequency Selection
Revision 3.01/August 2005 © Semtech Corp.
ADVANCED COMMUNICATIONS
Output
O1
Output
O2
FrSync
MFrSync
Frequency (MHz, unless stated otherwise)
2 kHz
2 kHz
8 kHz
8 kHz
Name
Port
TTL/CMOS
LVDS/PECL
(LVDS default)
TTL/CMOS
TTL/CMOS
Output Port
Technology
Frequency selection as per Table 7 and Table 11
FrSync, 8 kHz programmable pulse width and polarity, see Reg. 7A.
MFrSync, 2 kHz programmable pulse width and polarity, see Reg. 7A.
DPLL1 Mode
77.76 MHz Analog
Any digital feedback mode
77.76 MHz Analog
Any digital feedback mode
FINAL
Page 22
clocks are selectable from a range of pre-defined spot
frequencies/port technologies, as defined in Tables 6 and
7.
Outputs O1 & O2 Frequency Configuration Steps
The output frequency selection is performed in the
following steps:
6. Refer to Table 8, Frequency Divider Look-up, to
7. Refer to the Table 8 to determine the required APLL
8. Refer to Table 9, APLL1 Frequencies, and Table 10,
9. Refer to Table 11, O1 and O2 Output Frequency
Frequencies Supported
choose a set of output frequencies.
frequency to support the frequency set.
APLL2 Frequencies, to determine in what mode
DPLL1 and DPLL2 need to be configured, considering
the output jitter level.
Selection, and the column headings in Table 8,
Frequency Divider Look-up, to select the appropriate
frequency from either of the APLLs on each output as
required.
DPLL2 Mode
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-
-
-
APLL2 Input Mux
ACS8525 LC/P
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DATASHEET
www.semtech.com
Jitter Level (Typ)
1400
1400
rms
(ps)
60
60
(ns)
0.6
0.6
p-p
5
5