L64777 A LSI Logic Corporation, L64777 A Datasheet
L64777 A
Related parts for L64777 A
L64777 A Summary of contents
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... Two internal digital-to-analog converters generate in-phase and quadrature (I and Q) baseband signals. June 2000 Copyright © 2000 by LSI Logic Corporation. All rights reserved. shows a block diagram of a typical CATV transmitter using the QAM Mixer ...
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An on-chip voltage-controlled oscillator improves the symbol rate PLL to support most frequently used application ranges. A serial interface replaces the eight-bit microprocessor interface. A digital numerically controlled oscillator (NCO) and interpolation mode support operation with the L64724 device. The ...
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... The OCLK, which is four times the QAM symbol rate, is the base of all residual processing. L64777 DVB QAM Modulator Byte to Convol. Differential m-tuple Interleaver Encoder conversion is a block diagram of the L64777 architecture. The input clock Figure 3. I Square QAM Root Mapping Nyquist Q ...
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A numerically controlled oscillator (NCO) module allows the L64777 to interface with the LSI Logic L64724. In this case, the chip must receive the L64724 PCLK clock; thus, the byte_clock output from the L64724 must be applied to ICLK. This ...
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L64777 DVB QAM Modulator 5 ...
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PLL Modes Connecting the L64777 to a satellite receiver and the LSI Logic satellite decoder chipset requires the PLL circuits to lock the input and output clocks. Two modes can achieve this: Mode 1 uses the phase/frequency detector and the ...
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PLL Mode 2 In Mode 2, the PCLK input provides an external clock. The L64777 uses the internal NCO to lock to the transport byte clock, provided at ICLK. The chip generates an OCLK internally. Select PCLK ...
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Figure 6 Functional Test Bus (Test mode is selected using FT mode pins) The differential outputs terminate externally (the external components must provide termination to both differential lines, and the DAC achieves maximum linearity in differential mode). The L64777 I ...
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Control Interface An external CPU uses the L64777 serial control interface to control and setup the programmable parameters of the chip. This interface is a slave type only, connected to the same serial bus as the LSI Logic L64724. Serial ...
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Sync Acquisition Phase In the sync acquisition phase, the number of sync detections required for sync and loss is programmable from the designation for the number of track steps. After TS error-free consecutive detections of ...
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Figure 7 Read Pointer When specifying the microprocessor download value for the read pointer initialization, you must use Gray Code. The write pointer also is Gray Code counter-driven; it initializes to zero when the read counter is loaded. Properly programmed ...
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Energy Dispersal (Scrambler) Unit The function of the Scrambler is specified for the serial domain by the Digital Broadcasting Systems for Television Sound and Data Services: Framing Structure, Channel Coding and Modulation Cable Systems . The energy dispersal module (scrambler) ...
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... To achieve RS encoding at the lowest possible gate count and power consumption, the check byte parameters of the RS encoder in the L64777 are fixed 16, according to the DVB standard. When the RS encoder is switched off, data feeds through without check-word insertion at an internal delay of two clock cycles. ...
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... The values of the interleaver in the L64777 are 204 12, and M = 17. You can switch off the interleaver fully transparent with an intrinsic delay of three clock cycles. The main modules are a set of configured RAM-based delay lines to implement the proper delay for individual data bytes, and a controller to handle and generate the strobes needed by subsequent modules in the data path ...
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I and Q. For an oversampling factor of four, the filter executes the above sequence at four times the symbol rate (60 MHz in ...
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FIFO initialization. The microprocessor interface uses an I protocol. The interface is slave-only and can not be a master to the serial bus. The base address of the ...
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Figure 8 Logic Symbol for the L64777 DIN[7:0] DVALIDIN ERRORIN MPEG TS FSTARTIN MUX ICLK SCLK SSTARTIN VDD VSS L64777 DVB QAM Modulator Serial Microprocessor Interface L64777 QAM Modulator Control Signals External PLL Signals AVDD1 AVDD2 AVSS1 AVSS2 COMP1 COMP2 ...
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... FIFO. Clock Enable Input When DVALIDIN is active (HIGH), the L64777 accepts data from DIN[7: continuous basis. When DVALIDIN is LOW, data input to the internal FIFO and internal data processing stop, and the encoder does not accept new input from the DIN[7:0] pins ...
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SCLK SSTARTIN Status Information Signals DIG_I[9:0] DIG_Q[9:0] FIFOALARM FIRSTOUT FSTARTOUT Frame Start Output L64777 DVB QAM Modulator Modulator Symbol Clock Output SCLK is a clock output synchronous to internally processed symbols and bytes identical to OCLK/4. The L64777 ...
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SYNCOK Test Signals FTMODE[2:0] Functional Test Bus IDDTN[3] NT_OUT[4] SCAN_ENABLE[5] TNn[11] TRSTn[10] TMS[9] TDO[8] TDI[7] TCK[6] 20 L64777 DVB QAM Modulator number of bytes that the gap parameter inserts. A one-cycle width indicates no inserted gaps; a width of 17 ...
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Control Signals OCLK PLL_MODE[1:0] RESET_n External PLL Signals PCLK PLL_OUT_CS PLL Current Source Analog QAM Signals AVDD1 L64777 DVB QAM Modulator Encoder Out/Processing Clock In OCLK is a positive-edge-triggered clock. The L64777 internally processes data based on a fraction of ...
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AVDD2 AVSS1 AVSS2 COMP1 COMP2 IREF1 IREF2 QAM_I QAM_IN QAM_Q 22 L64777 DVB QAM Modulator Analog VDD Input: Q Component DAC Analog Input For usage and value, see the LSI Logic datasheet ® G10 -p CW900100 10-bit Direct Digital Synthesis ...
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... G10 -p CW900100 10-bit Direct Digital Synthesis Digital- to-Analog Converter (September 1998). Interrupt Request The L64777 asserts INT_n LOW when the interrupt is enabled and an interrupt condition occurs. INT_n is an open drain output that requires an external pull-up resistor for operation. Serial Bus Base Address ...
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... STG L64777 DVB QAM Modulator Serial Data Access In conjunction with SCL, SDA controls the microprocessor interface. Table 1 provides the L64777 absolute maximum Table 2 Table 3 L64777 Absolute Maximum Ratings Parameter DC Supply LVTTL Input Voltage 5 V Compatible Inputs DC Input Current Storage Temperature Range ...
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Table 2 Symbol When studying the values in LSI Logic G10 length. Table 3 L64777 DC Characteristics Symbol Parameter V Supply Voltage DD V Input Voltage LOW IL V Input Voltage HIGH IH V Output Voltage ...
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AC Timing Diagrams for L64777 Figure 9 Figure 9 ICLK Inputs Figure 10 Figure 10 RESET Figure 11 Figure 11 TN DATA Note: The numbers in column 1 of preceding figures. All parameters in this table apply for T 85 ...
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Table 4 L64777 Preliminary Timing Parameters No. Parameter Description 1 tCYCLE Clock Cycle OCLK 2 tPWH Clock Pulse Width HIGH OCLK 3 tPWL Clock Pulse Width LOW OCLK 4 tI_CYCLE Clock Cycle ICLK 5 tI_PWH Clock Pulse Width HIGH ICLK ...
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Table 5 Mnemonic AVDD1 AVDD2 AVSS1 AVSS2 COMP1 COMP2 DIG_I[9:0] DIG_Q[9:0] DIN[7:0] DVALIDIN ERRORIN FIFOALARM FIRSTOUT FSTARTIN FSTARTOUT FTMODE[2:0] GND ICLK IDDTN INT_n 28 L64777 DVB QAM Modulator L64777 Pin Description Summary Description Type Supply for DAC Analog Input Supply ...
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Table 5 L64777 Pin Description Summary (Cont.) Mnemonic Description IREF1 Reference Current Input IREF2 Reference Current Input NT_OUT Nand Tree OCLK VCO Clock Output or External Clock Input PCLK Clock Input for PLL Mode 2 PLL_MODE[1:0] Select PLL Mode PLL_OUT_CS ...
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Table 5 Mnemonic SSTARTIN SYNCOK TCK TDI TDO TMS TNn TRSTn VDDX_I VDDX_Q VREF_I VREF_Q 1. Also 5 V compatible. 30 L64777 DVB QAM Modulator L64777 Pin Description Summary (Cont.) Description Type Sequence Start Input TTL Input Sync Detection Flag ...
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Pin Lists for the L64777 Table 6 L64777 Numerical Pin List Signal Pin Signal VDD 1 PLL_MODE.0 VSS 2 PLL_MODE.1 QAM_I 3 IDDTN QAM_IN 4 TN AVDD1 5 RESET_N IREF1 6 VSS COMP1 7 DIG_Q.0 VREF_I 8 DIG_Q.1 AVSS 9 ...
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... Table 7 L64777 Alphabetical Pin List Signal Pin Signal AVDD1 5 DIN.4 AVDD2 16 DIN.5 AVSS 9 DIN.6 AVSS2 12 DIN.7 COMP1 7 DVALIDIN COMP2 14 ERRORIN DIG_I.0 106 FIFOALARM DIG_I.1 107 FIRSTOUT DIG_I.2 108 FSTARTIN DIG_I.3 109 FSTARTOUT DIG_I.4 110 FTMODE.0 DIG_I.5 112 FTMODE.1 DIG_I.6 113 FTMODE.2 DIG_I ...
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Package Pinout Figure 12 Package 120-Pin PQFP Pinout VDD 1 VSS 2 3 QAM_I 4 QAM_IN 5 AVDD1 6 IREF1 7 COMP1 8 VREF_I AVSS1 9 VDDX_I 10 VDDX_Q 11 12 AVSS2 13 VREF_Q 14 COMP2 15 IREF2 16 AVDD2 ...
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Figure 13 L64777. Figure 13 120-pin PQFP (PE) Mechanical Drawing Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline ...
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Figure 13 120-pin PQFP (PE) Mechanical Drawing (Cont.) Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for ...
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