L64777 A LSI Logic Corporation, L64777 A Datasheet - Page 6

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L64777 A

Manufacturer Part Number
L64777 A
Description
Communications, DVB QAM Modulator
Manufacturer
LSI Logic Corporation
Datasheet
PLL Modes
PLL Mode 1
Figure 5
Value
6
Load
CNT_I
ICLK
Phase and Frequency Detection with an External VCO
Connecting the L64777 to a satellite receiver and the LSI Logic satellite
decoder chipset requires the PLL circuits to lock the input and output
clocks. Two modes can achieve this:
Figure 5
voltage-controlled oscillator (VCO) loop. Choose between frequency and
phase detection through the microprocessor interface.
Prescalers (CNT_I) and a divider (CNT_O) in the feedback loop of the
PLL generate the internal operating clock (OCLK). Program the 15-bit
prescalers through the microprocessor interface, selecting values for
CNT_I and CNT_O that minimize CNT_O and reach the required ratio.
L64777 DVB QAM Modulator
%2
Mode 1 uses the phase/frequency detector and the dividers of the
L64777 to accept an external VCO.
Mode 2 connects the PCLK output of the L64724 or the L64734 to
the L64777 PCLK clock input, and connects the byte clock output to
the ICLK input of the L64777. This is also called the Numerically
Controlled Oscillator (NCO) mode of operation. This mode is
dedicated to the connection of the L64724.
FREQ_PHASE_COMP (From Microprocessor)
shows the phase and frequency detection for an external
Frequency Detect
Phase Detect
2
2
%2
From VCO
+Z current
CNT_O
OCLK
To VCO
PLL_CS
Load
Value

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