IDT82V2084 Integrated Device Technology, IDT82V2084 Datasheet
IDT82V2084
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IDT82V2084 Summary of contents
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... B8ZS/HDB3/AMI line encoding/decoding - Active edge of transmit clock (TCLK) and receive clock (RCLK) DESCRIPTION: The IDT82V2084 can be configured as a quad T1, quad E1 or quad J1 Line Interface Unit. In receive path, an Adaptive Equalizer is integrated to remove the distortion introduced by the cable attenuation. The IDT82V2084 also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and detects and reports the LOS conditions ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT FUNCTIONAL BLOCK DIAGRAM Figure-1 Block Diagram 2 INDUSTRIAL TEMPERATURE RANGES TDO TDI TMS TCK TRST RST REF THZ SCLKE INT/MOT P/S A[7:0] D[7:0] INT SDO SDI/R/W/WR DS/RD SCLK CS MCLKS MCLK ...
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... QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT TABLE OF CONTENTS TABLE OF CONTENTS 1 IDT82V2084 PIN CONFIGURATIONS .......................................................................................... 8 2 PIN DESCRIPTION ....................................................................................................................... 9 3 FUNCTIONAL DESCRIPTION .................................................................................................... 14 3.1 T1/E1/J1 MODE SELECTION .......................................................................................... 14 3.2 TRANSMIT PATH ............................................................................................................. 14 3.2.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 14 3.2.2 ENCODER .............................................................................................................. 14 3.2.3 PULSE SHAPER .................................................................................................... 14 3.2.3.1 Preset Pulse Templates .......................................................................... 14 3.2.3.2 LBO (Line Build Out) ............................................................................... 15 3.2.3.3 User-Programmable Arbitrary Waveform ................................................ 15 3 ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.8 ERROR DETECTION/COUNTING AND INSERTION ...................................................... 29 3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 29 3.8.2 ERROR DETECTION AND COUNTING ................................................................ 29 3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 30 ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT LIST OF TABLES Table-1 Pin Description ................................................................................................................ 9 Transmit Waveform Value For E1 75 Ω ........................................................................ 16 Table-2 Transmit Waveform Value For E1 120 Ω ...................................................................... 16 Table-3 Table-4 Transmit Waveform ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-41 MAINT2: Maintenance Function Control Register 2...................................................... 43 Table-42 MAINT3: Maintenance Function Control Register 3...................................................... 43 Table-43 MAINT4: Maintenance Function Control Register 4...................................................... 44 Table-44 MAINT5: Maintenance Function Control Register 5...................................................... ...
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... QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT LIST OF FIGURES Figure-1 Block Diagram ................................................................................................................. 2 Figure-2 IDT82V2084 TQFP128 Package Pin Assignment .......................................................... 8 Figure-3 E1 Waveform Template Diagram .................................................................................. 14 Figure-4 E1 Pulse Template Test Circuit ..................................................................................... 14 Figure-5 DSX-1 Waveform Template .......................................................................................... 14 Figure-6 T1 Pulse Template Test Circuit ..................................................................................... 15 Figure-7 Receive Path Function Block Diagram .......................................................................... 20 Figure-8 Transmit/Receive Line Circuit ...
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... RRING2 118 119 RTIP2 VDDR2 120 121 VDDA GNDA 122 123 TRST TMS 124 125 TDI TDO 126 127 TCK LOS1 128 Figure-2 IDT82V2084 TQFP128 Package Pin Assignment IDT82V2084 8 INDUSTRIAL TEMPERATURE RANGES 64 VDDR4 63 RTIP4 62 RRING4 61 GNDR4 60 GNDT4 59 GNDT4 58 TTIP4 57 TRING4 56 VDDT4 ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 2 PIN DESCRIPTION Table-1 Pin Description Name Type TQFP128 TTIP1 Output 104 1 TTIPn /TRINGn: Transmit Bipolar Tip/Ring for Channel 1~4 TTIP2 Analog 114 These pins are the differential line driver ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type TQFP128 RD1/RDP1 Output 93 RDn: Receive Data for Channel 1~4 RD2/RDP2 87 In Single Rail Mode, the NRZ receive data is output on these pins. ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type TQFP128 INT/MOT Input 6 INT/MOT: Intel or Motorola Microcontroller Interface Select In microcontroller mode, the parallel microcontroller interface is configured for Motorola compatible microcontrollers when ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type TQFP128 THZ Input 4 THZ: Transmit Driver Enable This pin enables or disables all transmitter drivers on a global basis. A low level on this ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type TQFP128 GNDR1 - 107 Analog Ground for Receiver GNDR2 117 GNDR3 51 GNDR4 IC: Internal Connection 7 Internal Use. These pins ...
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... QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3 FUNCTIONAL DESCRIPTION 3.1 T1/E1/J1 MODE SELECTION The IDT82V2084 can be used as a four-channel E1 LIU or a four-chan- nel T1/J1 LIU application, the T1E1 bit (GCF0, 40H) should be set to ‘0’. In T1/J1 application, the T1E1 bit should be set to ‘1’. 3.2 TRANSMIT PATH ...
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... QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT TTIPn IDT82V2084 TRINGn = 100 Ω ± 5% Note: R LOAD Figure-6 T1 Pulse Template Test Circuit For J1 applications, the PULS[3:0] (TCF1, 03H...) should be set to ‘0111’. Table-14 lists these values. 3.2.3.2 LBO (Line Build Out) To prevent the cross-talk at the far end, the output of TTIP/TRING could be attenuated before transmission for long haul applications ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-2 Transmit Waveform Value For E1 75 Ω Sample 0000000 0000000 2 0000000 0000000 3 0000000 0000000 4 0001100 0000000 5 0110000 0000000 6 0110000 0000000 ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-6 Transmit Waveform Value For T1 266~399 ft Sample 0011111 1000011 2 0110100 1000010 3 0101111 1000001 4 0101100 0000000 5 0101011 0000000 6 0101010 0000000 ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-10 Transmit Waveform Value For DS1 0 dB LBO Sample 0010111 1000010 2 0100111 1000001 3 0100111 0000000 4 0100110 0000000 5 0100101 0000000 6 0100101 ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.2.4 TRANSMIT PATH LINE INTERFACE The transmit line interface consists of TTIPn pin and TRINGn pin. The impedance matching can be realized by the internal impedance matching circuit or the external ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.3 RECEIVE PATH The receive path consists of Receive Internal Termination, Monitor Gain, Amplitude/Wave Shape Detector, Digital Tuning Controller, Adaptive Equalizer, Data Slicer, CDR (Clock and Data Recovery), Optional Jitter Attenuator, ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.3.2 LINE MONITOR In both T1/J1 and E1 short haul applications, the non-intrusive monitor- ing on channels located in other chips can be performed by tapping the mon- itored channel through ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.3.10 G.772 NON-INTRUSIVE MONITORING In applications using only three channels, channel 1 can be configured to monitor the data received or transmitted in any one of the remaining chan- nels. The ...
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... FIFO overflow and underflow, but the quality of jitter attenuation is deteriorated. RDn/RDPn 3.4.2 JITTER ATTENUATOR PERFORMANCE De-jittered Data The performance of the Jitter Attenuator in the IDT82V2084 meets the RDNn ITU-T I.431, G.703, G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/ 13, AT&T TR62411 specifications. Details of the Jitter Attenuator perfor- mance is shown in R Characteristics ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.5 LOS AND AIS DETECTION 3.5.1 LOS DETECTION The Loss of Signal Detector monitors the amplitude of the incoming sig- nal level and pulse density of the received signal on RTIPn ...
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... AIS DETECTION The Alarm Indication Signal can be detected by the IDT82V2084 when the Clock&Data Recovery unit is enabled. The status of AIS detection is reflected in the AIS_S bit (STAT0, 14H...). In T1/J1 applications, the criteria for declaring/clearing AIS detection are in compliance with the ANSI Table-19 AIS Condition ITU G.775 for E1 (LAC bit is set to ‘ ...
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... TRANSMIT AND DETECT INTERNAL PATTERNS The internal patterns (All Ones, All Zeros, PRBS/QRSS pattern and Activate/Deactivate Loopback Code) will be generated and detected by the IDT82V2084. TCLKn is used as the reference clock by default. MCLK can also be used as the reference clock by setting the PATT_CLK bit (MAINT0, 0AH...) to ‘1’. ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT LOS/AIS LOSn Detector B8ZS/ RCLKn RDn/RDPn HDB3/AMI CVn/RDNn Decoder B8ZS/ TCLKn TDn/TDPn HDB3/AMI Encoder TDNn LOS/AIS LOSn Detector B8ZS/ RCLKn Jitter RDn/RDPn HDB3/AMI Attenuator CVn/RDNn Decoder B8ZS/ TCLKn Jitter TDn/TDPn HDB3/AMI ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.7.4 INBAND LOOPBACK When PATT[1:0] bits (MAINT0, 0AH...) are set to ‘11’, the correspond- ing channel is configured in Inband Loopback mode. In this mode, an unframed activate/Deactivate Loopback Code is ...
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... ERROR DETECTION/COUNTING AND INSERTION 3.8.1 DEFINITION OF LINE CODING ERROR The following line encoding errors can be detected and counted by the IDT82V2084: • Received Bipolar Violation (BPV) Error: In AMI coding, when two consecutive pulses of the same polarity are received, a BPV error is declared. Table-21 EXZ Definition ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT • Manual Report Mode In Manual Report Mode, the internal Error Counter starts to count the received errors when the CNT_MD bit (MAINT6, 10H...) is set to ‘0’. When there is ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.10 MCLK AND TCLK 3.10.1 MASTER CLOCK (MCLK) MCLK is an independent, free-running reference clock. MCLK is 1.544 MHz or 37.056 MHz for T1/J1 applications and 2.048 MHz or 49.152 MHz ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.11 MICROCONTROLLER INTERFACES The microcontroller interface provides access to read and write the reg- isters in the device. The chip supports serial processor interface and two kinds of parallel processor interface: ...
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... QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.12 INTERRUPT HANDLING All kinds of interrupt of the IDT82V2084 are indicated by the INT pin. When the INT_PIN[0] bit (GCF0, 40H) is ‘0’, the INT pin is open drain active low, with a 10 KΩ external pull-up resistor. When the INT_PIN[1:0] bits (GCF0, 40H) are ‘ ...
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... PROGRAMMING INFORMATION 4.1 REGISTER LIST AND MAP The IDT82V2084 registers can be divided into Global Registers and Local Registers. The operation on the Global Registers affects all the four channels while the operation on Local Registers only affects that specific channel. For different channel, the address of Local Register is different. ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-24 Per Channel Register List and Map Address (Hex) Register R/W CH1-CH4 Jitter Attenuation Control Register 01,41,81,C1 JACF R/W Transmit Path Control Registers 02,42,82,C2 TCF0 R/W 03,43,83,C3 TCF1 R/W 04,44,84,C4 TCF2 ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 4.2 REGISTER DESCRIPTION 4.2.1 GLOBAL REGISTERS Table-25 ID: Chip Revision Register (R, Address = 00H) Symbol Bit Default ID[7:0] 7-0 01H Table-26 RST: Reset Register (W, Address = 20H) Symbol Bit ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-28 GCF1: Global Configuration Register 1 (R/W, Address = 60H) Symbol Bit Default MON[3:0] 7-4 0000 - 3-0 0000 Table-29 INTCH: Interrupt Channel Indication Register (R, Address = 80H) Symbol Bit ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 4.2.3 TRANSMIT PATH CONTROL REGISTERS Table-31 TCF0: Transmitter Configuration Register 0 (R/W, Address = 02H,42H,82H,C2H) Symbol Bit Default - 7-5 000 T_OFF 4 0 TD_INV 3 0 TCLK_SEL 2 0 T_MD[1:0] ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-33 TCF2: Transmitter Configuration Register 2 (R/W, Address = 04H,44H,84H,C4H) Symbol Bit Default - 7-6 00 SCAL[5:0] 5-0 100001 Table-34 TCF3: Transmitter Configuration Register 3 (R/W, Address = 05H,45H,85H,C5H) Symbol Bit ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 4.2.4 RECEIVE PATH CONTROL REGISTERS Table-36 RCF0: Receiver Configuration Register 0 (R/W, Address = 07H,47H,87H,C7H) Symbol Bit Default - 7-5 000 R_OFF 4 0 RD_INV 3 0 RCLK_SEL 2 0 R_MD[1:0] ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-37 RCF1: Receiver Configuration Register 1 (R/W, Address = 08H,48H,88H,C8H) Symbol Bit Default - 7 0 EQ_ON LOS[4:0] 4-0 10101 Reserved = 0: receive equalizer off ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-38 RCF2: Receiver Configuration Register 2 (R/W, Address =09H,49H,89H,C9H) Symbol Bit Default - 7-6 00 SLICE[1:0] 5-4 01 UPDW[1:0] 3-2 10 MG[1:0] 1-0 00 4.2.5 NETWORK DIAGNOSTICS CONTROL REGISTERS Table-39 MAINT0: ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-40 MAINT1: Maintenance Function Control Register 1 (R/W, Address = 0BH,4BH,8BH,CBH) Symbol Bit Default - 7-4 0000 ARLP 3 0 RLP 2 0 ALP 1 0 DLP 0 0 Table-41 MAINT2: ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-43 MAINT4: Maintenance Function Control Register 4 (R/W, Address = 0EH,4EH,8EH,CEH) Symbol Bit Default RIBLBA[7:0] 7-0 (000)00001 Defines the user-programmable receive Inband Loopback activate code. The default selection is 00001. Table-44 ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 4.2.6 INTERRUPT CONTROL REGISTERS Table-46 INTM0: Interrupt Mask Register 0 (R/W, Address = 11H,51H,91H,D1H) Symbol Bit Default EQ_IM 7 1 IBLBA_IM 6 1 IBLBD_IM 5 1 PRBS_IM 4 1 TCLK_IM 3 ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-47 INTM1: Interrupt Mask Register 1 (R/W, Address = 12H,52H,92H,D2H) Symbol Bit Default DAC_OV_IM 7 1 JAOV_IM 6 1 JAUD_IM 5 1 ERR_IM 4 1 EXZ_IM 3 1 CV_IM 2 1 ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-48 INTES: Interrupt Trigger Edges Select Register (R/W, Address = 13H, 53H,93H,D3H) Symbol Bit Default EQ_IES 7 0 IBLBA_IES 6 0 IBLBD_IES 5 0 PRBS_IES 4 0 TCLK_IES 3 0 DF_IES ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 4.2.7 LINE STATUS REGISTERS Table-49 STAT0: Line Status Register 0 (real time status monitor) (R, Address = 14H,54H,94H,D4H) Symbol Bit Default EQ_S 7 0 IBLBA_S 6 0 IBLBD_S 5 0 PRBS_S ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-49 STAT0: Line Status Register 0 (real time status monitor) (Continued) (R, Address = 14H,54H,94H,D4H) Symbol Bit Default DF_S 2 0 AIS_S 1 0 LOS_S 0 0 Line driver status indication ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-50 STAT1: Line Status Register 1 (real time status monitor) (R, Address = 15H, 55H,95H, D5H) Symbol Bit Default - 7-6 00 RLP_S 5 0 LATT[4:0] 4-0 00000 Reserved Indicating the ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 4.2.8 INTERRUPT STATUS REGISTERS Table-51 INTS0: Interrupt Status Register 0 (this register is reset after a read operation) (R, Address = 16H, 56H,96H, D6H) Symbol Bit Default EQ_IS 7 0 IBLBA_IS ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-52 INTS1: Interrupt Status Register 1 (this register is reset and relevant interrupt request is cleared after a read) (R, Address = 17H, 57H,97H, D7H) Symbol Bit Default DAC_OV_IS 7 0 ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 4.2.10 TRANSMIT AND RECEIVE TERMINATION REGISTER Table-55 TERM: Transmit and Receive Termination Configuration Register (R/W, Address = 1AH, 5AH,9AH,DAH) Symbol Bit Default - 7-6 00 T_TERM[2:0] 5-3 000 R_TERM[2:0] 2-0 000 ...
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... QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 5 IEEE STD 1149.1 JTAG TEST ACCESS PORT The IDT82V2084 supports the digital Boundary Scan Specification as described in the IEEE 1149.1 standards. The boundary scan architecture consists of data and instruction regis- ters plus a Test Access Port (TAP) controller. Control of the TAP is per- ...
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... Sample / Preload The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. The normal path between IDT82V2084 logic and the I/O pins is maintained. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 5.2.4 TEST ACCESS PORT CONTROLLER The TAP controller is a 16-state synchronous state machine. shows its state diagram following the description of each state. Note that the figure contains two main ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-58 TAP Controller State Description (Continued) STATE Pause-IR The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register selected ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 6 TEST SPECIFICATIONS Table-59 Absolute Maximum Rating Symbol VDDA, VDDD Core Power Supply VDDIO I/O Power Supply VDDT1-4 Transmit Power Supply VDDR1-4 Receive Power Supply Input Voltage, Any Digital Pin Input ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-61 Power Consumption Symbol Parameter E1, 3 Ω Load E1, 3.3 V, 120 Ω Load 3 T1, 3.3 V, 100 Ω Load J1, 3.3 V, 110 Ω Load 1.Maximum ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-63 E1 Receiver Electrical Characteristics Symbol Parameter Receiver sensitivity Short haul with cable loss@1024kHz: Long haul with cable loss@1024kHz: Analog LOS level Short haul Long haul Allowable consecutive zeros before LOS ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-64 T1/J1 Receiver Electrical Characteristics Symbol Parameter receiver sensitivity Short haul with cable loss@772kHz: Long haul with cable loss@772kHz: Analog LOS level Short haul Long haul Allowable consecutive zeros before LOS ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-65 E1 Transmitter Electrical Characteristics Symbol Vo-p Output pulse amplitudes E1, 75Ω load E1, 120Ω load Vo-s Zero (space) level E1, 75 Ω load E1, 120 Ω load Transmit amplitude variation ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-66 T1/J1 Transmitter Electrical Characteristics Symbol Vo-p Output pulse amplitudes Vo-s Zero (space) level Transmit amplitude variation with supply Difference between pulse sequences for 17 consecutive pulses(T1.102) TPW Output Pulse Width ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-67 Transmitter and Receiver Timing Characteristics Symbol Parameter MCLK frequency E1: T1/J1: MCLK tolerance MCLK duty cycle Transmit path TCLK frequency E1: T1/J1: TCLK tolerance TCLK Duty Cycle t1 Transmit Data ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT TCLKn TDn/TDPn TDNn RCLKn RDPn/RDn (RCLK_SEL = 0) RDNn/CVn RDPn/RDn (RCLK_SEL = 1) RDNn/CVn Table-68 Jitter Tolerance Jitter Tolerance E1 – 2.4 KHz 18 KHz – 100 ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Figure-25 E1 Jitter Tolerance Performance Figure-26 T1/J1 Jitter Tolerance Performance 66 INDUSTRIAL TEMPERATURE RANGES ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-69 Jitter Attenuator Characteristics Parameter Jitter Transfer Function Corner (-3dB) Frequency Jitter Attenuator E1: (G.736 400 Hz @ 100 kHz T1/J1: (Per AT&T pub.62411) ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Figure-27 E1 Jitter Transfer Performance Figure-28 T1/J1 Jitter Transfer Performance 68 INDUSTRIAL TEMPERATURE RANGES ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-70 JTAG Timing Characteristics Symbol t1 TCK Period t2 TMS to TCK Setup Time TDI to TCK Setup Time t3 TCK to TMS Hold Time TCK to TDI Hold Time t4 ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 7 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS 7.1 SERIAL INTERFACE TIMING Table-71 Serial Interface Timing Characteristics Symbol t1 SCLK High Time t2 SCLK Low Time t3 Active CS to SCLK Setup Time t4 ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 7.2 PARALLEL INTERFACE TIMING Table-72 Non_multiplexed Motorola Read Timing Characteristics Symbol tRC Read Cycle Time tDW Valid DS Width tRWV Delay from DS to Valid Read Signal tRWH R ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-73 Non_multiplexed Motorola Write Timing Characteristics Symbol tWC Write Cycle Time tDW Valid DS Width tRWV Delay from DS to Valid Write Signal tRWH R Hold Time tAV Delay ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-74 Non_multiplexed Intel Read Timing Characteristics Symbol tRC Read Cycle Time tRDW Valid RD Width tAV Delay from RD to Valid Address tAH Address to RD Hold Time tPRD RD to ...
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QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-75 Non_multiplexed Intel Write Timing Characteristics Symbol tWC Write Cycle Time tWRW Valid WR Width tAV Delay from WR to Valid Address tAH Address to WR Hold Time tDV Delay from ...
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... XX X Process/ Temperature Range for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* The IDT logo is a registered trademark of Integrated Device Technology, Inc. 75 TEMPERATURE RANGES Blank Industrial (-40 °C to +85 °C) Thin Quad Flatpack (TQFP, PK128) PF 82V2084 Long Haul/Short Haul LIU for Tech Support: 408-330-1753 email:TELECOMhelp@idt ...