IDT82V2084 Integrated Device Technology, IDT82V2084 Datasheet - Page 47

• Manufacturer Part Number: IDT82V2084
• Description: Quad Channel T1/e1/j1 Long Haul/ Short Haul Line Interface Unit
• Manufacturer: Integrated Device Technology

QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
Table-48 INTES: Interrupt Trigger Edges Select Register
IBLBA_IES
IBLBD_IES
PRBS_IES
TCLK_IES
LOS_IES
AIS_IES
Symbol
EQ_IES
DF_IES
(R/W, Address = 13H, 53H,93H,D3H)
Bit
6
5
4
7
3
2
1
0
Default
0
0
0
0
0
0
0
0
This bit determines the Inband Loopback Activate Code interrupt event.
This bit determines the Inband Loopback Deactivate Code interrupt event.
This bit determines the PRBS/QRSS synchronization status interrupt event.
This bit determines the Equalizer out of range interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the EQ_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the EQ_S bit in the STAT0
status register.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the IBLBA_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the IBLBA_S bit in the STAT0
status register.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the IBLBD_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the IBLBD_S bit in the STAT0
status register.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the PRBS_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the PRBS_S bit in the STAT0
status register.
This bit determines the TCLK Loss interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the TCLK_LOS bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the TCLK_LOS bit in the
STAT0 status register.
This bit determines the Driver Failure interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the DF_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the DF_S bit in the STAT0
status register.
This bit determines the AIS interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the AIS_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the AIS_S bit in the STAT0
status register.
This bit determines the LOS interrupt event.
= 0: interrupt event is defined as a ‘0’ to ‘1’ transition of the LOS_S bit in the STAT0 status register
= 1: interrupt event is defined as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the LOS_S bit in the STAT0
status register.
47
Description
TEMPERATURE RANGES
INDUSTRIAL