IDT82V3280 Integrated Device Technology, IDT82V3280 Datasheet - Page 50

• Manufacturer Part Number: IDT82V3280
• Description: Wan Pll
• Manufacturer: Integrated Device Technology

5.2
Table 33: Read Timing Characteristics in Multiplexed Mode
Microprocessor Interface
IDT82V3280
Note:
* Timing with RDY. If RDY is not used, t
Symbol
t
t
t
t
t
t
pw1
pw2
pw3
t
t
t
t
t
t
t
t
t
su1
su2
t
out
t
T
d1
d2
d4
d5
d6
h1
h2
h3
TI
in
T
MULTIPLEXED MODE
Time between consecutive Read-Read or Read-Write accesses
AD[7:0]
RDY
ALE
CS
WR
RD
RD rising edge to AD[7:0] high impedance delay time
Time between ALE falling edge and RD falling edge
Valid address after ALE falling edge hold time
Valid address to ALE falling edge setup time
pw1
CS rising edge to RDY release delay time
Valid RD after RDY rising edge hold time
Valid CS after RD rising edge hold time
RD rising edge to RDY low delay time
( RD rising edge to ALE rising edge)
is 3.5T + 10.
One cycle time of the master clock
Valid CS to valid RDY delay time
Valid RD to valid data delay time
Valid CS to Valid RD setup time
Valid ALE pulse width high
Valid RDY pulse width low
High-Z
Valid RD pulse width low
t
t
pw3
su1
Delay of output pad
Delay of input pad
address
Figure 17. Multiplexed Read Timing Diagram
Parameter
t
h1
t
d2
t
T
t
su2
t
d1
50
t
pw2
t
pw1
data
4.5T + 10 *
4.5T + 10
t
h3
Min
>T
2
0
2
3
0
0
0
t
d4
t
h2
t
d5
12.86
Typ
13
10
13
13
5
5
t
d6
High-Z
3.5T + 10
Max
June 19, 2006
WAN PLL
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns