IDT82V3280 Integrated Device Technology, IDT82V3280 Datasheet - Page 70
IDT82V3280
Manufacturer Part Number
IDT82V3280
Description
Wan Pll
Manufacturer
Integrated Device Technology
Datasheet
1.IDT82V3280.pdf
(167 pages)
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DIFFERENTIAL_IN_OUT_OSCI_CNFG - Differential Input / Output Port & Master Clock Configuration
Programming Information
IDT82V3280
Address: 0AH
Type: Read / Write
Default Value: XXXXX001
7 - 3
Bit
2
1
0
7
-
OUT7_PECL_LVDS
OUT6_PECL_LVDS
OSC_EDGE
Name
-
6
-
Reserved.
This bit selects a better active edge of the master clock.
0: The rising edge. (default)
1: The falling edge.
This bit selects a port technology for OUT7.
0: LVDS. (default)
1: PECL.
This bit selects a port technology for OUT6.
0: LVDS.
1: PECL. (default)
5
-
4
-
70
3
-
Description
OSC_EDGE
2
OUT7_PECL_LVDS
1
OUT6_PECL_LVDS
June 19, 2006
0
WAN PLL
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