74F162APC Fairchild Semiconductor, 74F162APC Datasheet - Page 2

• Manufacturer Part Number: 74F162APC
• Description: IC COUNTER SYNC PRESET BCD 16DIP
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr

Specifications of 74F162APC

• Logic Type: Counter, Decade
• Direction: Up
• Number Of Elements: 1
• Number Of Bits Per Element: 4
• Reset: Asynchronous
• Timing: Synchronous
• Count Rate: 120MHz
• Trigger Type: Positive Edge
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74F162

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Unit Loading/Fan Out
Functional Description
The 74F162A count modulo-10 in the BCD (8421)
sequence. From state 9 (HLLH) they increment to state 0
(LLLL). The clock inputs of all flip-flops are driven in paral-
lel through a clock buffer. Thus all changes of the Q outputs
occur as a result of, and synchronous with, the LOW-to-
HIGH transition of the CP input signal. The circuits have
four fundamental modes of operation, in order of prece-
dence: synchronous reset, parallel load, count-up and hold.
Four control inputs— Synchronous Reset (SR), Parallel
Enable (PE), Count Enable Parallel (CEP) and Count
Enable Trickle (CET)—determine the mode of operation,
as shown in the Mode Select Table. A LOW signal on SR
overrides counting and parallel loading and allows all out-
puts to go LOW on the next rising edge of CP. A LOW sig-
nal on PE overrides counting and allows information on the
Parallel Data (P
the next rising edge of CP. With PE and SR HIGH, CEP
and CET permit counting when both are HIGH. Conversely,
a LOW signal on either CEP or CET inhibits counting.
The F162A uses D-type edge-triggered flip-flops and
changing the SR, PE, CEP and CET inputs when the CP is
Mode Select Table
H
L
X
LOW Voltage Level
SR
HIGH Voltage Level
Immaterial
H
H
H
H
L
PE
X
H
H
H
L
CET CEP
n
X
X
H
X
Pin Names
CEP
CET
CP
SR
P
PE
Q
TC
L
) inputs to be loaded into the flip-flops on
0
0
–P
–Q
3
3
X
X
H
X
L
Reset (Clear)
Load (P
Count (Increment)
No Change (Hold)
No Change (Hold)
Count Enable Parallel Input
Count Enable Trickle Input
Clock Pulse Input (Active Rising Edge)
Synchronous Reset Input (Active LOW)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Flip-Flop Outputs
Terminal Count Output
Action on the Rising
Clock Edge (
n
Q
n
)
Description

)
2
in either state does not cause errors, provided that the rec-
ommended setup and hold times, with respect to the rising
edge of CP, are observed.
The Terminal Count (TC) output is HIGH when CET is
HIGH and counter is in state 9. To implement synchronous
multistage counters, the TC outputs can be used with the
CEP and CET inputs in two different ways. Please refer to
the F568 datasheet. The TC output is subject to decoding
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops, counters or registers. In the F162A decade
counters, the TC output is fully decoded and can only be
HIGH in state 9. If a decade counter is preset to an illegal
state, or assumes an illegal state when power is applied, it
will return to the normal sequence within two counts, as
shown in the State Diagram.
Logic Equations:
State Diagram
Count Enable
HIGH/LOW Output I
50/33.3
50/33.3
1.0/1.0
1.0/2.0
1.0/1.0
1.0/2.0
1.0/1.0
1.0/2.0
U.L.
TC
CEP
Q
20 A/ 0.6 mA
20 A/ 1.2 mA
20 A/ 0.6 mA
20 A/ 1.2 mA
20 A/ 0.6 mA
20 A/ 1.2 mA
0
Input I
1 mA/20 mA
1 mA/20 mA
Q
CET
1
IH
OH
Q
/I
/I
IL
2
OL
PE
Q
3
CET