MC10EL33DG ON Semiconductor, MC10EL33DG Datasheet - Page 5

• Manufacturer Part Number: MC10EL33DG
• Description: IC DIVIDER DIV X4 ECL DIFF 8SOIC
• Manufacturer: ON Semiconductor
• Series: 10ELr

Specifications of MC10EL33DG

• Logic Type: Divide-by-4
• Number Of Elements: 1
• Number Of Bits Per Element: 1
• Reset: Asynchronous
• Count Rate: 4.2GHz
• Trigger Type: Positive, Negative
• Voltage - Supply: 4.2 V ~ 5.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Mounting Style: SMD/SMT
• No. Of Inputs: 1
• Clock Frequency: 4GHz
• Supply Voltage Range: ± 4.2V To ± 5.7V
• Logic Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Direction: -
• Timing: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: MC10EL33DGOS

Table 7. AC CHARACTERISTICS
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
14. 10 Series: V
15. V
Symbol
f
t
t
t
V
t
t
t
max
PLH
PHL
RR
JITTER
r
f
PP
100 Series: V
PP
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.
Maximum Toggle Frequency
Propagation Delay
Set/Reset Recovery
Input Swing (Note 15)
Cycle−to−Cycle Jitter
Output Rise/Fall Times Q
(20% − 80%)
EE
RESET
EE
CLK
can vary +0.25 V / −0.5 V.
can vary +0.8 V / −0.5 V.
Q
Characteristic
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Driver
Device
Figure 3. Typical Termination for Output Driver and Device Evaluation
Reset to Q
CLK to Q
V
Q
Q
CC
= 5.0 V; V
Figure 2. Timing Diagram
Min
EE
560
400
400
150
100
3.4
Z
Z
= 0.0 V or V
http://onsemi.com
o
o
= 50 W
= 50 W
−40°C
Typ
670
540
200
225
4.2
1.0
50 W
V
5
TT
CC
1000
Max
= V
860
700
350
t
RR
= 0.0 V; V
V
CC
TT
− 2.0 V
50 W
Min
610
460
400
150
100
3.8
EE
= −5.0 V (Note 14)
25°C
Typ
700
550
200
225
4.2
1.0
D
D
1000
Max
810
660
350
Receiver
Device
Min
640
570
400
150
100
3.8
85°C
Typ
740
480
200
225
4.2
1.0
1000
Max
840
670
350
Unit
GHz
mV
ps
ps
ps
ps