MC54HC165 Motorola, MC54HC165 Datasheet - Page 4

MC54HC165

Manufacturer Part Number

MC54HC165

Description

8-Bit Serial or Parallel-Input/Serial-Output Shift Register

Manufacturer

Motorola

Datasheet

1.MC54HC165.pdf (8 pages)

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MOTOROLA

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

INPUTS

A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6)

nously entered in parallel into the internal flip–flops when the

Serial Shift/Parallel Load input is low.

SA (Pin 10)

is high, data on this pin is serially entered into the first stage

of the shift register with the rising edge of the Clock.

CONTROL INPUTS

Serial Shift/Parallel Load (Pin 1)

this pin, data at the Serial Data input (SA) are shifted into the

TIMING REQUIREMENTS

MC54/74HC165

Symbol

Parallel Data inputs. Data on these inputs are asynchro-

Serial Data input. When the Serial Shift/Parallel Load input

Data–entry control input. When a high level is applied to

t rec

t r , t f

t su

t w

t h

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Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load

Minimum Setup Time, Input SA to Clock (or Clock Inhibit)

Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit)

Minimum Setup Time, Clock to Clock Inhibit

Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs

Minimum Hold Time, Clock (or Clock Inhibit) to Input SA

Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load

Minimum Recovery Time, Clock to Clock Inhibit

Minimum Pulse Width, Clock (or Clock Inhibit)

Minimum Pulse width, Serial Shift/Parallel Load

Maximum Input Rise and Fall Times

(Figure 4)

(Figure 5)

(Figure 6)

(Figure 7)

(Figure 4)

(Figure 5)

(Figure 6)

(Figure 7)

(Figure 1)

(Figure 2)

(Figure 1)

(Input t r = t f = 6 ns)

Parameter

PIN DESCRIPTIONS

applied to this pin, data at the Parallel Data inputs are

asynchronously loaded into each of the eight internal stages.

Clock, Clock Inhibit (Pins 2, 15)

Either may be used as an active–high clock inhibit. However,

to avoid double clocking, the inhibit input should go high only

while the clock input is high.

down to DC in a continuous or intermittent mode.

OUTPUTS

Q H , Q H (Pins 9, 7)

noninverted and inverted outputs of the eighth stage of the

shift register.

Clock inputs. These two clock inputs function identically.

The shift register is completely static, allowing Clock rates

Complementary Shift Register outputs. These pins are the

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V CC

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

2.0

4.5

6.0

Î Î Î Î Î Î Î Î Î

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– 55 to

25 _ C

1000

100

500

400

Guaranteed Limit

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High–Speed CMOS Logic Data

1000

125

100

500

400

85 _ C

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1000

125 _ C

150

120

500

400

DL129 — Rev 6

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Unit

MC54HC165 Motorola, MC54HC165 Datasheet - Page 4

MC54HC165

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