CY7C4245V-15ASXC Cypress Semiconductor Corp, CY7C4245V-15ASXC Datasheet - Page 14

• Manufacturer Part Number: CY7C4245V-15ASXC
• Description: IC SYNC FIFO MEM 4KX18 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4245V-15ASXC

• Access Time: 10ns
• Memory Size: 72K (4K x 18)
• Package / Case: 64-LQFP
• Function: Synchronous
• Data Rate: 67MHz
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Data Bus Width: 18 bit
• Bus Direction: Unidirectional
• Timing Type: Synchronous
• Organization: 4 K x 18
• Maximum Clock Frequency: 66.7 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 30 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1716

Document #: 38-06029 Rev. *C
Switching Waveforms
Programmable Almost Empty Flag Timing
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)
Notes:
20. PAE offset − n. Number of data words into FIFO already = n.
21. PAE offset − n.
22. t
23. If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
WCLK and the rising RCLK is less than t
SKEW3
PAE
WEN
WCLK
WCLK
RCLK
RCLK
WEN
REN
REN
PAE
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
[20]
t
CLKH
(continued)
t
SKEW3
SKEW3
t
CLKH
t
, then PAE may not change state until the next RCLK.
ENS
[22]
t
ENH
t
CLKL
Note 21
t
ENS
t
ENH
t
t
PAEsynch
CLKL
t
PAE
t
t
ENS
ENS
n+1 WORDS
N + 1 WORDS
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
IN FIFO
INFIFO
t
ENS
t
PAE
t
ENH
n WORDS IN FIFO
Note 23
Page 14 of 20
t
PAEsynch
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