CY7C4245V-15ASXC Cypress Semiconductor Corp, CY7C4245V-15ASXC Datasheet - Page 3

• Manufacturer Part Number: CY7C4245V-15ASXC
• Description: IC SYNC FIFO MEM 4KX18 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4245V-15ASXC

• Access Time: 10ns
• Memory Size: 72K (4K x 18)
• Package / Case: 64-LQFP
• Function: Synchronous
• Data Rate: 67MHz
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Data Bus Width: 18 bit
• Bus Direction: Unidirectional
• Timing Type: Synchronous
• Organization: 4 K x 18
• Maximum Clock Frequency: 66.7 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 30 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1716

Document #: 38-06029 Rev. *C
Selection Guide
Pin Definitions
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Operating Current
Density
Packages
D
Q
WEN
REN
WCLK
RCLK
WXO/HF
EF
FF
PAE
PAF
LD
FL/RT
WXI
RXI
Signal Name
0−17
0−17
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
Read Clock
Write Expansion
Out/Half Full Flag
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Load
First Load/
Retransmit
Write Expansion
Input
Read Expansion
Input
64-pin 14x14
64-pin 10x10
CY7C4425V
Description
64 x 18
STQFP
TQFP
Commercial
64-pin 14x14
64-pin 10x10
CY7C4205V
I/O
O Data outputs for an 18-bit bus.
O Dual-Mode Pin. Single device or width expansion - Half Full status flag. Cascaded –
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty
O When PAF is LOW, the FIFO is almost full based on the almost full offset
I
I
I
I
I
I
I
I
I
256 x 18
STQFP
TQFP
Data inputs for an 18-bit bus.
Enables the WCLK input.
Enables the RCLK input.
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is
not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is
not Empty. When LD is asserted, RCLK reads data out of the programmable
flag-offset register.
Write Expansion Out signal, connected to WXI of next device.
offset value programmed into the FIFO. PAE is asynchronous when
V
to V
value programmed into the FIFO. PAF is asynchronous when V
tied to V
When LD is LOW, D
mable-flag-offset register.
Dual-Mode Pin. Cascaded – The first device in the daisy chain will have FL tied to
V
expansion, FL is tied to V
function is also available in standalone mode by strobing RT.
Cascaded – Connected to WXO of previous device. Not Cascaded – Tied to V
Cascaded – Connected to RXO of previous device. Not Cascaded – Tied to V
CC
SS
; all other devices will have FL tied to V
/SMODE is tied to V
SS
.
CC
; it is synchronized to WCLK when V
CY7C42X5V-15
64-pin 14x14
64-pin 10x10
CY7C4215V
512 x 18
STQFP
TQFP
66.7
15
30
11
11
4
1
0−17
CC
SS
(O
; it is synchronized to RCLK when V
on all devices. Not Cascaded – Tied to V
0−17
64-pin 14x14
64-pin 10x10
CY7C4225V
) are written (read) into (from) the program-
CY7C42X5V-25
1K x 18
STQFP
TQFP
Function
40
15
25
15
30
6
1
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
CC
. In standard mode of width
CC
64-pin 14x14
64-pin 10x10
CY7C4235V
/SMODE is tied to V
2K x 18
STQFP
TQFP
CY7C42X5V-35
28.6
20
35
20
30
7
2
CC
/SMODE is tied
CC
SS
64-pin 14x14
64-pin 10x10
CY7C4245V
/SMODE is
. Retransmit
Page 3 of 20
4K x 18
STQFP
TQFP
SS
.
Unit
MHz
mA
ns
ns
ns
ns
ns
SS
SS
.
.
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