IDT72255LA10PF IDT, Integrated Device Technology Inc, IDT72255LA10PF Datasheet - Page 3

• Manufacturer Part Number: IDT72255LA10PF
• Description: IC FIFO SUPERSYNC 8KX18 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72255LA10PF

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Access Time: 10ns
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 8ns
• Word Size: 18b
• Organization: 8Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 80mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72255LA10PF; 800-1499

DESCRIPTION (CONTINUED)
the data output lines after three transitions of the RCLK signal. A REN does not
have to be asserted for accessing the first word. However, subsequent words
written to the FIFO do require a LOW on REN for access. The state of the FWFT/
SI input during Master Reset determines the timing mode in use.
provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-
Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF functions
are selected in IDT Standard mode. The IR and OR functions are selected in
FWFT mode. HF, PAE and PAF are always available for use, irrespective of
timing mode.
memory. (See Table I and Table 2.) Programmable offsets determine the flag
switching threshold and can be loaded by two methods: parallel or serial. Two
default offset settings are also provided, so that PAE can be set to switch at 127
or 1,023 locations from the empty boundary and the PAF threshold can be set
at 127 or 1,023 locations from the full boundary. These choices are made with
the LD pin during Master Reset.
are used to load the offset registers via the Serial Input (SI). For parallel
IDT72255LA/72265LA CMOS SuperSync FIFO™
8,192 x 18 and 16,384 x 18
In FWFT mode, the first word written to an empty FIFO is clocked directly to
For applications requiring more data storage capacity than a single FIFO can
PAE and PAF can be programmed independently to switch at any point in
For serial programming, SEN together with LD on each rising edge of WCLK,
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/
FIRST WORD FALL THROUGH/SERIAL INPUT
PROGRAMMABLE ALMOST-FULL (PAF)
FULL FLAG/INPUT READY (FF/IR)
Figure 1. Block Diagram of Single 8,192 x 18 and 16,384 x 18 Synchronous FIFO
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
SERIAL ENABLE(SEN)
DATA IN ( D
PARTIAL RESET (PRS)
LOAD (LD)
(FWFT/SI)
0
- D
n
)
72255LA
72265LA
3
IDT
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via Dn. REN together with LD on each rising edge
of RCLK can be used to read the offsets in parallel from Qn regardless of whether
serial or parallel offset loading has been selected.
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode. The LD pin selects either a partial flag default
setting of 127 with parallel programming or a partial flag default setting of 1,023
with serial programming. The flags are updated according to the timing mode
and default offsets selected.
location of the memory. However, the timing mode, partial flag programming
method, and default or programmed offset settings existing before Partial Reset
remain unchanged. The flags are updated according to the timing mode and
offsets in effect. PRS is useful for resetting a device in mid-operation, when
reprogramming partial flags would be undesirable.
once. A LOW on the RT input during a rising RCLK edge initiates a retransmit
operation by setting the read pointer to the first location of the memory array.
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
cron CMOS technology.
During Master Reset (MRS) the following events occur: The read and write
The Partial Reset (PRS) also sets the read and write pointers to the first
The Retransmit function allows data to be reread from the FIFO more than
If, at any time, the FIFO is not actively performing an operation, the chip will
The IDT72255LA/72265LA are fabricated using IDT’s high speed submi-
MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF FULL FLAG (HF)
DATA OUT ( Q
OUTPUT ENABLE (OE)
0
- Q
n
COMMERCIAL AND INDUSTRIAL
)
TEMPERATURE RANGES
JANUARY 13, 2009
4670 drw03